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[1.6]001 /* CPU data for frv. 002 003 THIS FILE IS MACHINE GENERATED WITH CGEN. 004 005 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. 006 007 This file is part of the GNU Binutils and/or GDB, the GNU debugger. 008 009 This program is free software; you can redistribute it and/or modify 010 it under the terms of the GNU General Public License as published by 011 the Free Software Foundation; either version 2, or (at your option) 012 any later version. 013 014 This program is distributed in the hope that it will be useful, 015 but WITHOUT ANY WARRANTY; without even the implied warranty of 016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 017 GNU General Public License for more details. 018 019 You should have received a copy of the GNU General Public License along 020 with this program; if not, write to the Free Software Foundation, Inc., 021 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 022 023 */ 024 025 #include "sysdep.h" 026 #include <stdio.h> 027 #include <stdarg.h> 028 #include "ansidecl.h" 029 #include "bfd.h" 030 #include "symcat.h" 031 #include "frv-desc.h" 032 #include "frv-opc.h" 033 #include "opintl.h" 034 #include "libiberty.h" 035 #include "xregex.h" 036 037 /* Attributes. */ 038 039 static const CGEN_ATTR_ENTRY bool_attr[] = 040 { 041 { "#f", 0 }, 042 { "#t", 1 }, 043 { 0, 0 } 044 }; 045 046 static const CGEN_ATTR_ENTRY MACH_attr[] = 047 { 048 { "base", MACH_BASE }, 049 { "frv", MACH_FRV }, 050 { "fr550", MACH_FR550 }, 051 { "fr500", MACH_FR500 }, 052 { "fr400", MACH_FR400 }, 053 { "tomcat", MACH_TOMCAT }, 054 { "simple", MACH_SIMPLE }, 055 { "max", MACH_MAX }, 056 { 0, 0 } 057 }; 058 059 static const CGEN_ATTR_ENTRY ISA_attr[] = 060 { 061 { "frv", ISA_FRV }, 062 { "max", ISA_MAX }, 063 { 0, 0 } 064 }; 065 066 static const CGEN_ATTR_ENTRY UNIT_attr[] = 067 { 068 { "NIL", UNIT_NIL }, 069 { "I0", UNIT_I0 }, 070 { "I1", UNIT_I1 }, 071 { "I01", UNIT_I01 }, 072 { "I2", UNIT_I2 }, 073 { "I3", UNIT_I3 }, 074 { "IALL", UNIT_IALL }, 075 { "FM0", UNIT_FM0 }, 076 { "FM1", UNIT_FM1 }, 077 { "FM01", UNIT_FM01 }, 078 { "FM2", UNIT_FM2 }, 079 { "FM3", UNIT_FM3 }, 080 { "FMALL", UNIT_FMALL }, 081 { "FMLOW", UNIT_FMLOW }, 082 { "B0", UNIT_B0 }, 083 { "B1", UNIT_B1 }, 084 { "B01", UNIT_B01 }, 085 { "C", UNIT_C }, 086 { "MULT_DIV", UNIT_MULT_DIV }, 087 { "IACC", UNIT_IACC }, 088 { "LOAD", UNIT_LOAD }, 089 { "STORE", UNIT_STORE }, 090 { "SCAN", UNIT_SCAN }, 091 { "DCPL", UNIT_DCPL }, 092 { "MDUALACC", UNIT_MDUALACC }, 093 { "MCLRACC_1", UNIT_MCLRACC_1 }, 094 { "NUM_UNITS", UNIT_NUM_UNITS }, 095 { 0, 0 } 096 }; 097 098 static const CGEN_ATTR_ENTRY FR400_MAJOR_attr[] = 099 { 100 { "NONE", FR400_MAJOR_NONE }, 101 { "I_1", FR400_MAJOR_I_1 }, 102 { "I_2", FR400_MAJOR_I_2 }, 103 { "I_3", FR400_MAJOR_I_3 }, 104 { "I_4", FR400_MAJOR_I_4 }, 105 { "I_5", FR400_MAJOR_I_5 }, 106 { "B_1", FR400_MAJOR_B_1 }, 107 { "B_2", FR400_MAJOR_B_2 }, 108 { "B_3", FR400_MAJOR_B_3 }, 109 { "B_4", FR400_MAJOR_B_4 }, 110 { "B_5", FR400_MAJOR_B_5 }, 111 { "B_6", FR400_MAJOR_B_6 }, 112 { "C_1", FR400_MAJOR_C_1 }, 113 { "C_2", FR400_MAJOR_C_2 }, 114 { "M_1", FR400_MAJOR_M_1 }, 115 { "M_2", FR400_MAJOR_M_2 }, 116 { 0, 0 } 117 }; 118 119 static const CGEN_ATTR_ENTRY FR500_MAJOR_attr[] = 120 { 121 { "NONE", FR500_MAJOR_NONE }, 122 { "I_1", FR500_MAJOR_I_1 }, 123 { "I_2", FR500_MAJOR_I_2 }, 124 { "I_3", FR500_MAJOR_I_3 }, 125 { "I_4", FR500_MAJOR_I_4 }, 126 { "I_5", FR500_MAJOR_I_5 }, 127 { "I_6", FR500_MAJOR_I_6 }, 128 { "B_1", FR500_MAJOR_B_1 }, 129 { "B_2", FR500_MAJOR_B_2 }, 130 { "B_3", FR500_MAJOR_B_3 }, 131 { "B_4", FR500_MAJOR_B_4 }, 132 { "B_5", FR500_MAJOR_B_5 }, 133 { "B_6", FR500_MAJOR_B_6 }, 134 { "C_1", FR500_MAJOR_C_1 }, 135 { "C_2", FR500_MAJOR_C_2 }, 136 { "F_1", FR500_MAJOR_F_1 }, 137 { "F_2", FR500_MAJOR_F_2 }, 138 { "F_3", FR500_MAJOR_F_3 }, 139 { "F_4", FR500_MAJOR_F_4 }, 140 { "F_5", FR500_MAJOR_F_5 }, 141 { "F_6", FR500_MAJOR_F_6 }, 142 { "F_7", FR500_MAJOR_F_7 }, 143 { "F_8", FR500_MAJOR_F_8 }, 144 { "M_1", FR500_MAJOR_M_1 }, 145 { "M_2", FR500_MAJOR_M_2 }, 146 { "M_3", FR500_MAJOR_M_3 }, 147 { "M_4", FR500_MAJOR_M_4 }, 148 { "M_5", FR500_MAJOR_M_5 }, 149 { "M_6", FR500_MAJOR_M_6 }, 150 { "M_7", FR500_MAJOR_M_7 }, 151 { "M_8", FR500_MAJOR_M_8 }, 152 { 0, 0 } 153 }; 154 155 static const CGEN_ATTR_ENTRY FR550_MAJOR_attr[] = 156 { 157 { "NONE", FR550_MAJOR_NONE }, 158 { "I_1", FR550_MAJOR_I_1 }, 159 { "I_2", FR550_MAJOR_I_2 }, 160 { "I_3", FR550_MAJOR_I_3 }, 161 { "I_4", FR550_MAJOR_I_4 }, 162 { "I_5", FR550_MAJOR_I_5 }, 163 { "I_6", FR550_MAJOR_I_6 }, 164 { "I_7", FR550_MAJOR_I_7 }, 165 { "I_8", FR550_MAJOR_I_8 }, 166 { "B_1", FR550_MAJOR_B_1 }, 167 { "B_2", FR550_MAJOR_B_2 }, 168 { "B_3", FR550_MAJOR_B_3 }, 169 { "B_4", FR550_MAJOR_B_4 }, 170 { "B_5", FR550_MAJOR_B_5 }, 171 { "B_6", FR550_MAJOR_B_6 }, 172 { "C_1", FR550_MAJOR_C_1 }, 173 { "C_2", FR550_MAJOR_C_2 }, 174 { "F_1", FR550_MAJOR_F_1 }, 175 { "F_2", FR550_MAJOR_F_2 }, 176 { "F_3", FR550_MAJOR_F_3 }, 177 { "F_4", FR550_MAJOR_F_4 }, 178 { "M_1", FR550_MAJOR_M_1 }, 179 { "M_2", FR550_MAJOR_M_2 }, 180 { "M_3", FR550_MAJOR_M_3 }, 181 { "M_4", FR550_MAJOR_M_4 }, 182 { "M_5", FR550_MAJOR_M_5 }, 183 { 0, 0 } 184 }; 185 186 const CGEN_ATTR_TABLE frv_cgen_ifield_attr_table[] = 187 { 188 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 189 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 190 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 191 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 192 { "RESERVED", &bool_attr[0], &bool_attr[0] }, 193 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 194 { "SIGNED", &bool_attr[0], &bool_attr[0] }, 195 { 0, 0, 0 } 196 }; 197 198 const CGEN_ATTR_TABLE frv_cgen_hardware_attr_table[] = 199 { 200 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 201 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 202 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, 203 { "PC", &bool_attr[0], &bool_attr[0] }, 204 { "PROFILE", &bool_attr[0], &bool_attr[0] }, 205 { 0, 0, 0 } 206 }; 207 208 const CGEN_ATTR_TABLE frv_cgen_operand_attr_table[] = 209 { 210 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 211 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 212 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 213 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 214 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 215 { "SIGNED", &bool_attr[0], &bool_attr[0] }, 216 { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, 217 { "RELAX", &bool_attr[0], &bool_attr[0] }, 218 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, 219 { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] }, 220 { 0, 0, 0 } 221 }; 222 223 const CGEN_ATTR_TABLE frv_cgen_insn_attr_table[] = 224 { 225 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 226 { "UNIT", & UNIT_attr[0], & UNIT_attr[0] }, 227 { "FR400-MAJOR", & FR400_MAJOR_attr[0], & FR400_MAJOR_attr[0] }, 228 { "FR500-MAJOR", & FR500_MAJOR_attr[0], & FR500_MAJOR_attr[0] }, 229 { "FR550-MAJOR", & FR550_MAJOR_attr[0], & FR550_MAJOR_attr[0] }, 230 { "ALIAS", &bool_attr[0], &bool_attr[0] }, 231 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 232 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, 233 { "COND-CTI", &bool_attr[0], &bool_attr[0] }, 234 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, 235 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, 236 { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, 237 { "RELAXED", &bool_attr[0], &bool_attr[0] }, 238 { "NO-DIS", &bool_attr[0], &bool_attr[0] }, 239 { "PBB", &bool_attr[0], &bool_attr[0] }, 240 { "PRIVILEGED", &bool_attr[0], &bool_attr[0] }, 241 { "NON-EXCEPTING", &bool_attr[0], &bool_attr[0] }, 242 { "CONDITIONAL", &bool_attr[0], &bool_attr[0] }, 243 { "FR-ACCESS", &bool_attr[0], &bool_attr[0] }, 244 { "PRESERVE-OVF", &bool_attr[0], &bool_attr[0] }, 245 { 0, 0, 0 } 246 }; 247 248 /* Instruction set variants. */ 249 250 static const CGEN_ISA frv_cgen_isa_table[] = { 251 { "frv", 32, 32, 32, 32 }, 252 { 0, 0, 0, 0, 0 } 253 }; 254 255 /* Machine variants. */ 256 257 static const CGEN_MACH frv_cgen_mach_table[] = { 258 { "frv", "frv", MACH_FRV, 0 }, 259 { "fr550", "fr550", MACH_FR550, 0 }, 260 { "fr500", "fr500", MACH_FR500, 0 }, 261 { "tomcat", "tomcat", MACH_TOMCAT, 0 }, 262 { "fr400", "fr400", MACH_FR400, 0 }, 263 { "simple", "simple", MACH_SIMPLE, 0 }, 264 { 0, 0, 0, 0 } 265 }; 266 267 static CGEN_KEYWORD_ENTRY frv_cgen_opval_gr_names_entries[] = 268 { 269 { "sp", 1, {0, {0}}, 0, 0 }, 270 { "fp", 2, {0, {0}}, 0, 0 }, 271 { "gr0", 0, {0, {0}}, 0, 0 }, 272 { "gr1", 1, {0, {0}}, 0, 0 }, 273 { "gr2", 2, {0, {0}}, 0, 0 }, 274 { "gr3", 3, {0, {0}}, 0, 0 }, 275 { "gr4", 4, {0, {0}}, 0, 0 }, 276 { "gr5", 5, {0, {0}}, 0, 0 }, 277 { "gr6", 6, {0, {0}}, 0, 0 }, 278 { "gr7", 7, {0, {0}}, 0, 0 }, 279 { "gr8", 8, {0, {0}}, 0, 0 }, 280 { "gr9", 9, {0, {0}}, 0, 0 }, 281 { "gr10", 10, {0, {0}}, 0, 0 }, 282 { "gr11", 11, {0, {0}}, 0, 0 }, 283 { "gr12", 12, {0, {0}}, 0, 0 }, 284 { "gr13", 13, {0, {0}}, 0, 0 }, 285 { "gr14", 14, {0, {0}}, 0, 0 }, 286 { "gr15", 15, {0, {0}}, 0, 0 }, 287 { "gr16", 16, {0, {0}}, 0, 0 }, 288 { "gr17", 17, {0, {0}}, 0, 0 }, 289 { "gr18", 18, {0, {0}}, 0, 0 }, 290 { "gr19", 19, {0, {0}}, 0, 0 }, 291 { "gr20", 20, {0, {0}}, 0, 0 }, 292 { "gr21", 21, {0, {0}}, 0, 0 }, 293 { "gr22", 22, {0, {0}}, 0, 0 }, 294 { "gr23", 23, {0, {0}}, 0, 0 }, 295 { "gr24", 24, {0, {0}}, 0, 0 }, 296 { "gr25", 25, {0, {0}}, 0, 0 }, 297 { "gr26", 26, {0, {0}}, 0, 0 }, 298 { "gr27", 27, {0, {0}}, 0, 0 }, 299 { "gr28", 28, {0, {0}}, 0, 0 }, 300 { "gr29", 29, {0, {0}}, 0, 0 }, 301 { "gr30", 30, {0, {0}}, 0, 0 }, 302 { "gr31", 31, {0, {0}}, 0, 0 }, 303 { "gr32", 32, {0, {0}}, 0, 0 }, 304 { "gr33", 33, {0, {0}}, 0, 0 }, 305 { "gr34", 34, {0, {0}}, 0, 0 }, 306 { "gr35", 35, {0, {0}}, 0, 0 }, 307 { "gr36", 36, {0, {0}}, 0, 0 }, 308 { "gr37", 37, {0, {0}}, 0, 0 }, 309 { "gr38", 38, {0, {0}}, 0, 0 }, 310 { "gr39", 39, {0, {0}}, 0, 0 }, 311 { "gr40", 40, {0, {0}}, 0, 0 }, 312 { "gr41", 41, {0, {0}}, 0, 0 }, 313 { "gr42", 42, {0, {0}}, 0, 0 }, 314 { "gr43", 43, {0, {0}}, 0, 0 }, 315 { "gr44", 44, {0, {0}}, 0, 0 }, 316 { "gr45", 45, {0, {0}}, 0, 0 }, 317 { "gr46", 46, {0, {0}}, 0, 0 }, 318 { "gr47", 47, {0, {0}}, 0, 0 }, 319 { "gr48", 48, {0, {0}}, 0, 0 }, 320 { "gr49", 49, {0, {0}}, 0, 0 }, 321 { "gr50", 50, {0, {0}}, 0, 0 }, 322 { "gr51", 51, {0, {0}}, 0, 0 }, 323 { "gr52", 52, {0, {0}}, 0, 0 }, 324 { "gr53", 53, {0, {0}}, 0, 0 }, 325 { "gr54", 54, {0, {0}}, 0, 0 }, 326 { "gr55", 55, {0, {0}}, 0, 0 }, 327 { "gr56", 56, {0, {0}}, 0, 0 }, 328 { "gr57", 57, {0, {0}}, 0, 0 }, 329 { "gr58", 58, {0, {0}}, 0, 0 }, 330 { "gr59", 59, {0, {0}}, 0, 0 }, 331 { "gr60", 60, {0, {0}}, 0, 0 }, 332 { "gr61", 61, {0, {0}}, 0, 0 }, 333 { "gr62", 62, {0, {0}}, 0, 0 }, 334 { "gr63", 63, {0, {0}}, 0, 0 } 335 }; 336 337 CGEN_KEYWORD frv_cgen_opval_gr_names = 338 { 339 & frv_cgen_opval_gr_names_entries[0], 340 66, 341 0, 0, 0, 0, "" 342 }; 343 344 static CGEN_KEYWORD_ENTRY frv_cgen_opval_fr_names_entries[] = 345 { 346 { "fr0", 0, {0, {0}}, 0, 0 }, 347 { "fr1", 1, {0, {0}}, 0, 0 }, 348 { "fr2", 2, {0, {0}}, 0, 0 }, 349 { "fr3", 3, {0, {0}}, 0, 0 }, 350 { "fr4", 4, {0, {0}}, 0, 0 }, 351 { "fr5", 5, {0, {0}}, 0, 0 }, 352 { "fr6", 6, {0, {0}}, 0, 0 }, 353 { "fr7", 7, {0, {0}}, 0, 0 }, 354 { "fr8", 8, {0, {0}}, 0, 0 }, 355 { "fr9", 9, {0, {0}}, 0, 0 }, 356 { "fr10", 10, {0, {0}}, 0, 0 }, 357 { "fr11", 11, {0, {0}}, 0, 0 }, 358 { "fr12", 12, {0, {0}}, 0, 0 }, 359 { "fr13", 13, {0, {0}}, 0, 0 }, 360 { "fr14", 14, {0, {0}}, 0, 0 }, 361 { "fr15", 15, {0, {0}}, 0, 0 }, 362 { "fr16", 16, {0, {0}}, 0, 0 }, 363 { "fr17", 17, {0, {0}}, 0, 0 }, 364 { "fr18", 18, {0, {0}}, 0, 0 }, 365 { "fr19", 19, {0, {0}}, 0, 0 }, 366 { "fr20", 20, {0, {0}}, 0, 0 }, 367 { "fr21", 21, {0, {0}}, 0, 0 }, 368 { "fr22", 22, {0, {0}}, 0, 0 }, 369 { "fr23", 23, {0, {0}}, 0, 0 }, 370 { "fr24", 24, {0, {0}}, 0, 0 }, 371 { "fr25", 25, {0, {0}}, 0, 0 }, 372 { "fr26", 26, {0, {0}}, 0, 0 }, 373 { "fr27", 27, {0, {0}}, 0, 0 }, 374 { "fr28", 28, {0, {0}}, 0, 0 }, 375 { "fr29", 29, {0, {0}}, 0, 0 }, 376 { "fr30", 30, {0, {0}}, 0, 0 }, 377 { "fr31", 31, {0, {0}}, 0, 0 }, 378 { "fr32", 32, {0, {0}}, 0, 0 }, 379 { "fr33", 33, {0, {0}}, 0, 0 }, 380 { "fr34", 34, {0, {0}}, 0, 0 }, 381 { "fr35", 35, {0, {0}}, 0, 0 }, 382 { "fr36", 36, {0, {0}}, 0, 0 }, 383 { "fr37", 37, {0, {0}}, 0, 0 }, 384 { "fr38", 38, {0, {0}}, 0, 0 }, 385 { "fr39", 39, {0, {0}}, 0, 0 }, 386 { "fr40", 40, {0, {0}}, 0, 0 }, 387 { "fr41", 41, {0, {0}}, 0, 0 }, 388 { "fr42", 42, {0, {0}}, 0, 0 }, 389 { "fr43", 43, {0, {0}}, 0, 0 }, 390 { "fr44", 44, {0, {0}}, 0, 0 }, 391 { "fr45", 45, {0, {0}}, 0, 0 }, 392 { "fr46", 46, {0, {0}}, 0, 0 }, 393 { "fr47", 47, {0, {0}}, 0, 0 }, 394 { "fr48", 48, {0, {0}}, 0, 0 }, 395 { "fr49", 49, {0, {0}}, 0, 0 }, 396 { "fr50", 50, {0, {0}}, 0, 0 }, 397 { "fr51", 51, {0, {0}}, 0, 0 }, 398 { "fr52", 52, {0, {0}}, 0, 0 }, 399 { "fr53", 53, {0, {0}}, 0, 0 }, 400 { "fr54", 54, {0, {0}}, 0, 0 }, 401 { "fr55", 55, {0, {0}}, 0, 0 }, 402 { "fr56", 56, {0, {0}}, 0, 0 }, 403 { "fr57", 57, {0, {0}}, 0, 0 }, 404 { "fr58", 58, {0, {0}}, 0, 0 }, 405 { "fr59", 59, {0, {0}}, 0, 0 }, 406 { "fr60", 60, {0, {0}}, 0, 0 }, 407 { "fr61", 61, {0, {0}}, 0, 0 }, 408 { "fr62", 62, {0, {0}}, 0, 0 }, 409 { "fr63", 63, {0, {0}}, 0, 0 } 410 }; 411 412 CGEN_KEYWORD frv_cgen_opval_fr_names = 413 { 414 & frv_cgen_opval_fr_names_entries[0], 415 64, 416 0, 0, 0, 0, "" 417 }; 418 419 static CGEN_KEYWORD_ENTRY frv_cgen_opval_cpr_names_entries[] = 420 { 421 { "cpr0", 0, {0, {0}}, 0, 0 }, 422 { "cpr1", 1, {0, {0}}, 0, 0 }, 423 { "cpr2", 2, {0, {0}}, 0, 0 }, 424 { "cpr3", 3, {0, {0}}, 0, 0 }, 425 { "cpr4", 4, {0, {0}}, 0, 0 }, 426 { "cpr5", 5, {0, {0}}, 0, 0 }, 427 { "cpr6", 6, {0, {0}}, 0, 0 }, 428 { "cpr7", 7, {0, {0}}, 0, 0 }, 429 { "cpr8", 8, {0, {0}}, 0, 0 }, 430 { "cpr9", 9, {0, {0}}, 0, 0 }, 431 { "cpr10", 10, {0, {0}}, 0, 0 }, 432 { "cpr11", 11, {0, {0}}, 0, 0 }, 433 { "cpr12", 12, {0, {0}}, 0, 0 }, 434 { "cpr13", 13, {0, {0}}, 0, 0 }, 435 { "cpr14", 14, {0, {0}}, 0, 0 }, 436 { "cpr15", 15, {0, {0}}, 0, 0 }, 437 { "cpr16", 16, {0, {0}}, 0, 0 }, 438 { "cpr17", 17, {0, {0}}, 0, 0 }, 439 { "cpr18", 18, {0, {0}}, 0, 0 }, 440 { "cpr19", 19, {0, {0}}, 0, 0 }, 441 { "cpr20", 20, {0, {0}}, 0, 0 }, 442 { "cpr21", 21, {0, {0}}, 0, 0 }, 443 { "cpr22", 22, {0, {0}}, 0, 0 }, 444 { "cpr23", 23, {0, {0}}, 0, 0 }, 445 { "cpr24", 24, {0, {0}}, 0, 0 }, 446 { "cpr25", 25, {0, {0}}, 0, 0 }, 447 { "cpr26", 26, {0, {0}}, 0, 0 }, 448 { "cpr27", 27, {0, {0}}, 0, 0 }, 449 { "cpr28", 28, {0, {0}}, 0, 0 }, 450 { "cpr29", 29, {0, {0}}, 0, 0 }, 451 { "cpr30", 30, {0, {0}}, 0, 0 }, 452 { "cpr31", 31, {0, {0}}, 0, 0 }, 453 { "cpr32", 32, {0, {0}}, 0, 0 }, 454 { "cpr33", 33, {0, {0}}, 0, 0 }, 455 { "cpr34", 34, {0, {0}}, 0, 0 }, 456 { "cpr35", 35, {0, {0}}, 0, 0 }, 457 { "cpr36", 36, {0, {0}}, 0, 0 }, 458 { "cpr37", 37, {0, {0}}, 0, 0 }, 459 { "cpr38", 38, {0, {0}}, 0, 0 }, 460 { "cpr39", 39, {0, {0}}, 0, 0 }, 461 { "cpr40", 40, {0, {0}}, 0, 0 }, 462 { "cpr41", 41, {0, {0}}, 0, 0 }, 463 { "cpr42", 42, {0, {0}}, 0, 0 }, 464 { "cpr43", 43, {0, {0}}, 0, 0 }, 465 { "cpr44", 44, {0, {0}}, 0, 0 }, 466 { "cpr45", 45, {0, {0}}, 0, 0 }, 467 { "cpr46", 46, {0, {0}}, 0, 0 }, 468 { "cpr47", 47, {0, {0}}, 0, 0 }, 469 { "cpr48", 48, {0, {0}}, 0, 0 }, 470 { "cpr49", 49, {0, {0}}, 0, 0 }, 471 { "cpr50", 50, {0, {0}}, 0, 0 }, 472 { "cpr51", 51, {0, {0}}, 0, 0 }, 473 { "cpr52", 52, {0, {0}}, 0, 0 }, 474 { "cpr53", 53, {0, {0}}, 0, 0 }, 475 { "cpr54", 54, {0, {0}}, 0, 0 }, 476 { "cpr55", 55, {0, {0}}, 0, 0 }, 477 { "cpr56", 56, {0, {0}}, 0, 0 }, 478 { "cpr57", 57, {0, {0}}, 0, 0 }, 479 { "cpr58", 58, {0, {0}}, 0, 0 }, 480 { "cpr59", 59, {0, {0}}, 0, 0 }, 481 { "cpr60", 60, {0, {0}}, 0, 0 }, 482 { "cpr61", 61, {0, {0}}, 0, 0 }, 483 { "cpr62", 62, {0, {0}}, 0, 0 }, 484 { "cpr63", 63, {0, {0}}, 0, 0 } 485 }; 486 487 CGEN_KEYWORD frv_cgen_opval_cpr_names = 488 { 489 & frv_cgen_opval_cpr_names_entries[0], 490 64, 491 0, 0, 0, 0, "" 492 }; 493 494 static CGEN_KEYWORD_ENTRY frv_cgen_opval_spr_names_entries[] = 495 { 496 { "psr", 0, {0, {0}}, 0, 0 }, 497 { "pcsr", 1, {0, {0}}, 0, 0 }, 498 { "bpcsr", 2, {0, {0}}, 0, 0 }, 499 { "tbr", 3, {0, {0}}, 0, 0 }, 500 { "bpsr", 4, {0, {0}}, 0, 0 }, 501 { "hsr0", 16, {0, {0}}, 0, 0 }, 502 { "hsr1", 17, {0, {0}}, 0, 0 }, 503 { "hsr2", 18, {0, {0}}, 0, 0 }, 504 { "hsr3", 19, {0, {0}}, 0, 0 }, 505 { "hsr4", 20, {0, {0}}, 0, 0 }, 506 { "hsr5", 21, {0, {0}}, 0, 0 }, 507 { "hsr6", 22, {0, {0}}, 0, 0 }, 508 { "hsr7", 23, {0, {0}}, 0, 0 }, 509 { "hsr8", 24, {0, {0}}, 0, 0 }, 510 { "hsr9", 25, {0, {0}}, 0, 0 }, 511 { "hsr10", 26, {0, {0}}, 0, 0 }, 512 { "hsr11", 27, {0, {0}}, 0, 0 }, 513 { "hsr12", 28, {0, {0}}, 0, 0 }, 514 { "hsr13", 29, {0, {0}}, 0, 0 }, 515 { "hsr14", 30, {0, {0}}, 0, 0 }, 516 { "hsr15", 31, {0, {0}}, 0, 0 }, 517 { "hsr16", 32, {0, {0}}, 0, 0 }, 518 { "hsr17", 33, {0, {0}}, 0, 0 }, 519 { "hsr18", 34, {0, {0}}, 0, 0 }, 520 { "hsr19", 35, {0, {0}}, 0, 0 }, 521 { "hsr20", 36, {0, {0}}, 0, 0 }, 522 { "hsr21", 37, {0, {0}}, 0, 0 }, 523 { "hsr22", 38, {0, {0}}, 0, 0 }, 524 { "hsr23", 39, {0, {0}}, 0, 0 }, 525 { "hsr24", 40, {0, {0}}, 0, 0 }, 526 { "hsr25", 41, {0, {0}}, 0, 0 }, 527 { "hsr26", 42, {0, {0}}, 0, 0 }, 528 { "hsr27", 43, {0, {0}}, 0, 0 }, 529 { "hsr28", 44, {0, {0}}, 0, 0 }, 530 { "hsr29", 45, {0, {0}}, 0, 0 }, 531 { "hsr30", 46, {0, {0}}, 0, 0 }, 532 { "hsr31", 47, {0, {0}}, 0, 0 }, 533 { "hsr32", 48, {0, {0}}, 0, 0 }, 534 { "hsr33", 49, {0, {0}}, 0, 0 }, 535 { "hsr34", 50, {0, {0}}, 0, 0 }, 536 { "hsr35", 51, {0, {0}}, 0, 0 }, 537 { "hsr36", 52, {0, {0}}, 0, 0 }, 538 { "hsr37", 53, {0, {0}}, 0, 0 }, 539 { "hsr38", 54, {0, {0}}, 0, 0 }, 540 { "hsr39", 55, {0, {0}}, 0, 0 }, 541 { "hsr40", 56, {0, {0}}, 0, 0 }, 542 { "hsr41", 57, {0, {0}}, 0, 0 }, 543 { "hsr42", 58, {0, {0}}, 0, 0 }, 544 { "hsr43", 59, {0, {0}}, 0, 0 }, 545 { "hsr44", 60, {0, {0}}, 0, 0 }, 546 { "hsr45", 61, {0, {0}}, 0, 0 }, 547 { "hsr46", 62, {0, {0}}, 0, 0 }, 548 { "hsr47", 63, {0, {0}}, 0, 0 }, 549 { "hsr48", 64, {0, {0}}, 0, 0 }, 550 { "hsr49", 65, {0, {0}}, 0, 0 }, 551 { "hsr50", 66, {0, {0}}, 0, 0 }, 552 { "hsr51", 67, {0, {0}}, 0, 0 }, 553 { "hsr52", 68, {0, {0}}, 0, 0 }, 554 { "hsr53", 69, {0, {0}}, 0, 0 }, 555 { "hsr54", 70, {0, {0}}, 0, 0 }, 556 { "hsr55", 71, {0, {0}}, 0, 0 }, 557 { "hsr56", 72, {0, {0}}, 0, 0 }, 558 { "hsr57", 73, {0, {0}}, 0, 0 }, 559 { "hsr58", 74, {0, {0}}, 0, 0 }, 560 { "hsr59", 75, {0, {0}}, 0, 0 }, 561 { "hsr60", 76, {0, {0}}, 0, 0 }, 562 { "hsr61", 77, {0, {0}}, 0, 0 }, 563 { "hsr62", 78, {0, {0}}, 0, 0 }, 564 { "hsr63", 79, {0, {0}}, 0, 0 }, 565 { "ccr", 256, {0, {0}}, 0, 0 }, 566 { "cccr", 263, {0, {0}}, 0, 0 }, 567 { "lr", 272, {0, {0}}, 0, 0 }, 568 { "lcr", 273, {0, {0}}, 0, 0 }, 569 { "iacc0h", 280, {0, {0}}, 0, 0 }, 570 { "iacc0l", 281, {0, {0}}, 0, 0 }, 571 { "isr", 288, {0, {0}}, 0, 0 }, 572 { "neear0", 352, {0, {0}}, 0, 0 }, 573 { "neear1", 353, {0, {0}}, 0, 0 }, 574 { "neear2", 354, {0, {0}}, 0, 0 }, 575 { "neear3", 355, {0, {0}}, 0, 0 }, 576 { "neear4", 356, {0, {0}}, 0, 0 }, 577 { "neear5", 357, {0, {0}}, 0, 0 }, 578 { "neear6", 358, {0, {0}}, 0, 0 }, 579 { "neear7", 359, {0, {0}}, 0, 0 }, 580 { "neear8", 360, {0, {0}}, 0, 0 }, 581 { "neear9", 361, {0, {0}}, 0, 0 }, 582 { "neear10", 362, {0, {0}}, 0, 0 }, 583 { "neear11", 363, {0, {0}}, 0, 0 }, 584 { "neear12", 364, {0, {0}}, 0, 0 }, 585 { "neear13", 365, {0, {0}}, 0, 0 }, 586 { "neear14", 366, {0, {0}}, 0, 0 }, 587 { "neear15", 367, {0, {0}}, 0, 0 }, 588 { "neear16", 368, {0, {0}}, 0, 0 }, 589 { "neear17", 369, {0, {0}}, 0, 0 }, 590 { "neear18", 370, {0, {0}}, 0, 0 }, 591 { "neear19", 371, {0, {0}}, 0, 0 }, 592 { "neear20", 372, {0, {0}}, 0, 0 }, 593 { "neear21", 373, {0, {0}}, 0, 0 }, 594 { "neear22", 374, {0, {0}}, 0, 0 }, 595 { "neear23", 375, {0, {0}}, 0, 0 }, 596 { "neear24", 376, {0, {0}}, 0, 0 }, 597 { "neear25", 377, {0, {0}}, 0, 0 }, 598 { "neear26", 378, {0, {0}}, 0, 0 }, 599 { "neear27", 379, {0, {0}}, 0, 0 }, 600 { "neear28", 380, {0, {0}}, 0, 0 }, 601 { "neear29", 381, {0, {0}}, 0, 0 }, 602 { "neear30", 382, {0, {0}}, 0, 0 }, 603 { "neear31", 383, {0, {0}}, 0, 0 }, 604 { "nesr0", 384, {0, {0}}, 0, 0 }, 605 { "nesr1", 385, {0, {0}}, 0, 0 }, 606 { "nesr2", 386, {0, {0}}, 0, 0 }, 607 { "nesr3", 387, {0, {0}}, 0, 0 }, 608 { "nesr4", 388, {0, {0}}, 0, 0 }, 609 { "nesr5", 389, {0, {0}}, 0, 0 }, 610 { "nesr6", 390, {0, {0}}, 0, 0 }, 611 { "nesr7", 391, {0, {0}}, 0, 0 }, 612 { "nesr8", 392, {0, {0}}, 0, 0 }, 613 { "nesr9", 393, {0, {0}}, 0, 0 }, 614 { "nesr10", 394, {0, {0}}, 0, 0 }, 615 { "nesr11", 395, {0, {0}}, 0, 0 }, 616 { "nesr12", 396, {0, {0}}, 0, 0 }, 617 { "nesr13", 397, {0, {0}}, 0, 0 }, 618 { "nesr14", 398, {0, {0}}, 0, 0 }, 619 { "nesr15", 399, {0, {0}}, 0, 0 }, 620 { "nesr16", 400, {0, {0}}, 0, 0 }, 621 { "nesr17", 401, {0, {0}}, 0, 0 }, 622 { "nesr18", 402, {0, {0}}, 0, 0 }, 623 { "nesr19", 403, {0, {0}}, 0, 0 }, 624 { "nesr20", 404, {0, {0}}, 0, 0 }, 625 { "nesr21", 405, {0, {0}}, 0, 0 }, 626 { "nesr22", 406, {0, {0}}, 0, 0 }, 627 { "nesr23", 407, {0, {0}}, 0, 0 }, 628 { "nesr24", 408, {0, {0}}, 0, 0 }, 629 { "nesr25", 409, {0, {0}}, 0, 0 }, 630 { "nesr26", 410, {0, {0}}, 0, 0 }, 631 { "nesr27", 411, {0, {0}}, 0, 0 }, 632 { "nesr28", 412, {0, {0}}, 0, 0 }, 633 { "nesr29", 413, {0, {0}}, 0, 0 }, 634 { "nesr30", 414, {0, {0}}, 0, 0 }, 635 { "nesr31", 415, {0, {0}}, 0, 0 }, 636 { "necr", 416, {0, {0}}, 0, 0 }, 637 { "gner0", 432, {0, {0}}, 0, 0 }, 638 { "gner1", 433, {0, {0}}, 0, 0 }, 639 { "fner0", 434, {0, {0}}, 0, 0 }, 640 { "fner1", 435, {0, {0}}, 0, 0 }, 641 { "epcr0", 512, {0, {0}}, 0, 0 }, 642 { "epcr1", 513, {0, {0}}, 0, 0 }, 643 { "epcr2", 514, {0, {0}}, 0, 0 }, 644 { "epcr3", 515, {0, {0}}, 0, 0 }, 645 { "epcr4", 516, {0, {0}}, 0, 0 }, 646 { "epcr5", 517, {0, {0}}, 0, 0 }, 647 { "epcr6", 518, {0, {0}}, 0, 0 }, 648 { "epcr7", 519, {0, {0}}, 0, 0 }, 649 { "epcr8", 520, {0, {0}}, 0, 0 }, 650 { "epcr9", 521, {0, {0}}, 0, 0 }, 651 { "epcr10", 522, {0, {0}}, 0, 0 }, 652 { "epcr11", 523, {0, {0}}, 0, 0 }, 653 { "epcr12", 524, {0, {0}}, 0, 0 }, 654 { "epcr13", 525, {0, {0}}, 0, 0 }, 655 { "epcr14", 526, {0, {0}}, 0, 0 }, 656 { "epcr15", 527, {0, {0}}, 0, 0 }, 657 { "epcr16", 528, {0, {0}}, 0, 0 }, 658 { "epcr17", 529, {0, {0}}, 0, 0 }, 659 { "epcr18", 530, {0, {0}}, 0, 0 }, 660 { "epcr19", 531, {0, {0}}, 0, 0 }, 661 { "epcr20", 532, {0, {0}}, 0, 0 }, 662 { "epcr21", 533, {0, {0}}, 0, 0 }, 663 { "epcr22", 534, {0, {0}}, 0, 0 }, 664 { "epcr23", 535, {0, {0}}, 0, 0 }, 665 { "epcr24", 536, {0, {0}}, 0, 0 }, 666 { "epcr25", 537, {0, {0}}, 0, 0 }, 667 { "epcr26", 538, {0, {0}}, 0, 0 }, 668 { "epcr27", 539, {0, {0}}, 0, 0 }, 669 { "epcr28", 540, {0, {0}}, 0, 0 }, 670 { "epcr29", 541, {0, {0}}, 0, 0 }, 671 { "epcr30", 542, {0, {0}}, 0, 0 }, 672 { "epcr31", 543, {0, {0}}, 0, 0 }, 673 { "epcr32", 544, {0, {0}}, 0, 0 }, 674 { "epcr33", 545, {0, {0}}, 0, 0 }, 675 { "epcr34", 546, {0, {0}}, 0, 0 }, 676 { "epcr35", 547, {0, {0}}, 0, 0 }, 677 { "epcr36", 548, {0, {0}}, 0, 0 }, 678 { "epcr37", 549, {0, {0}}, 0, 0 }, 679 { "epcr38", 550, {0, {0}}, 0, 0 }, 680 { "epcr39", 551, {0, {0}}, 0, 0 }, 681 { "epcr40", 552, {0, {0}}, 0, 0 }, 682 { "epcr41", 553, {0, {0}}, 0, 0 }, 683 { "epcr42", 554, {0, {0}}, 0, 0 }, 684 { "epcr43", 555, {0, {0}}, 0, 0 }, 685 { "epcr44", 556, {0, {0}}, 0, 0 }, 686 { "epcr45", 557, {0, {0}}, 0, 0 }, 687 { "epcr46", 558, {0, {0}}, 0, 0 }, 688 { "epcr47", 559, {0, {0}}, 0, 0 }, 689 { "epcr48", 560, {0, {0}}, 0, 0 }, 690 { "epcr49", 561, {0, {0}}, 0, 0 }, 691 { "epcr50", 562, {0, {0}}, 0, 0 }, 692 { "epcr51", 563, {0, {0}}, 0, 0 }, 693 { "epcr52", 564, {0, {0}}, 0, 0 }, 694 { "epcr53", 565, {0, {0}}, 0, 0 }, 695 { "epcr54", 566, {0, {0}}, 0, 0 }, 696 { "epcr55", 567, {0, {0}}, 0, 0 }, 697 { "epcr56", 568, {0, {0}}, 0, 0 }, 698 { "epcr57", 569, {0, {0}}, 0, 0 }, 699 { "epcr58", 570, {0, {0}}, 0, 0 }, 700 { "epcr59", 571, {0, {0}}, 0, 0 }, 701 { "epcr60", 572, {0, {0}}, 0, 0 }, 702 { "epcr61", 573, {0, {0}}, 0, 0 }, 703 { "epcr62", 574, {0, {0}}, 0, 0 }, 704 { "epcr63", 575, {0, {0}}, 0, 0 }, 705 { "esr0", 576, {0, {0}}, 0, 0 }, 706 { "esr1", 577, {0, {0}}, 0, 0 }, 707 { "esr2", 578, {0, {0}}, 0, 0 }, 708 { "esr3", 579, {0, {0}}, 0, 0 }, 709 { "esr4", 580, {0, {0}}, 0, 0 }, 710 { "esr5", 581, {0, {0}}, 0, 0 }, 711 { "esr6", 582, {0, {0}}, 0, 0 }, 712 { "esr7", 583, {0, {0}}, 0, 0 }, 713 { "esr8", 584, {0, {0}}, 0, 0 }, 714 { "esr9", 585, {0, {0}}, 0, 0 }, 715 { "esr10", 586, {0, {0}}, 0, 0 }, 716 { "esr11", 587, {0, {0}}, 0, 0 }, 717 { "esr12", 588, {0, {0}}, 0, 0 }, 718 { "esr13", 589, {0, {0}}, 0, 0 }, 719 { "esr14", 590, {0, {0}}, 0, 0 }, 720 { "esr15", 591, {0, {0}}, 0, 0 }, 721 { "esr16", 592, {0, {0}}, 0, 0 }, 722 { "esr17", 593, {0, {0}}, 0, 0 }, 723 { "esr18", 594, {0, {0}}, 0, 0 }, 724 { "esr19", 595, {0, {0}}, 0, 0 }, 725 { "esr20", 596, {0, {0}}, 0, 0 }, 726 { "esr21", 597, {0, {0}}, 0, 0 }, 727 { "esr22", 598, {0, {0}}, 0, 0 }, 728 { "esr23", 599, {0, {0}}, 0, 0 }, 729 { "esr24", 600, {0, {0}}, 0, 0 }, 730 { "esr25", 601, {0, {0}}, 0, 0 }, 731 { "esr26", 602, {0, {0}}, 0, 0 }, 732 { "esr27", 603, {0, {0}}, 0, 0 }, 733 { "esr28", 604, {0, {0}}, 0, 0 }, 734 { "esr29", 605, {0, {0}}, 0, 0 }, 735 { "esr30", 606, {0, {0}}, 0, 0 }, 736 { "esr31", 607, {0, {0}}, 0, 0 }, 737 { "esr32", 608, {0, {0}}, 0, 0 }, 738 { "esr33", 609, {0, {0}}, 0, 0 }, 739 { "esr34", 610, {0, {0}}, 0, 0 }, 740 { "esr35", 611, {0, {0}}, 0, 0 }, 741 { "esr36", 612, {0, {0}}, 0, 0 }, 742 { "esr37", 613, {0, {0}}, 0, 0 }, 743 { "esr38", 614, {0, {0}}, 0, 0 }, 744 { "esr39", 615, {0, {0}}, 0, 0 }, 745 { "esr40", 616, {0, {0}}, 0, 0 }, 746 { "esr41", 617, {0, {0}}, 0, 0 }, 747 { "esr42", 618, {0, {0}}, 0, 0 }, 748 { "esr43", 619, {0, {0}}, 0, 0 }, 749 { "esr44", 620, {0, {0}}, 0, 0 }, 750 { "esr45", 621, {0, {0}}, 0, 0 }, 751 { "esr46", 622, {0, {0}}, 0, 0 }, 752 { "esr47", 623, {0, {0}}, 0, 0 }, 753 { "esr48", 624, {0, {0}}, 0, 0 }, 754 { "esr49", 625, {0, {0}}, 0, 0 }, 755 { "esr50", 626, {0, {0}}, 0, 0 }, 756 { "esr51", 627, {0, {0}}, 0, 0 }, 757 { "esr52", 628, {0, {0}}, 0, 0 }, 758 { "esr53", 629, {0, {0}}, 0, 0 }, 759 { "esr54", 630, {0, {0}}, 0, 0 }, 760 { "esr55", 631, {0, {0}}, 0, 0 }, 761 { "esr56", 632, {0, {0}}, 0, 0 }, 762 { "esr57", 633, {0, {0}}, 0, 0 }, 763 { "esr58", 634, {0, {0}}, 0, 0 }, 764 { "esr59", 635, {0, {0}}, 0, 0 }, 765 { "esr60", 636, {0, {0}}, 0, 0 }, 766 { "esr61", 637, {0, {0}}, 0, 0 }, 767 { "esr62", 638, {0, {0}}, 0, 0 }, 768 { "esr63", 639, {0, {0}}, 0, 0 }, 769 { "eir0", 640, {0, {0}}, 0, 0 }, 770 { "eir1", 641, {0, {0}}, 0, 0 }, 771 { "eir2", 642, {0, {0}}, 0, 0 }, 772 { "eir3", 643, {0, {0}}, 0, 0 }, 773 { "eir4", 644, {0, {0}}, 0, 0 }, 774 { "eir5", 645, {0, {0}}, 0, 0 }, 775 { "eir6", 646, {0, {0}}, 0, 0 }, 776 { "eir7", 647, {0, {0}}, 0, 0 }, 777 { "eir8", 648, {0, {0}}, 0, 0 }, 778 { "eir9", 649, {0, {0}}, 0, 0 }, 779 { "eir10", 650, {0, {0}}, 0, 0 }, 780 { "eir11", 651, {0, {0}}, 0, 0 }, 781 { "eir12", 652, {0, {0}}, 0, 0 }, 782 { "eir13", 653, {0, {0}}, 0, 0 }, 783 { "eir14", 654, {0, {0}}, 0, 0 }, 784 { "eir15", 655, {0, {0}}, 0, 0 }, 785 { "eir16", 656, {0, {0}}, 0, 0 }, 786 { "eir17", 657, {0, {0}}, 0, 0 }, 787 { "eir18", 658, {0, {0}}, 0, 0 }, 788 { "eir19", 659, {0, {0}}, 0, 0 }, 789 { "eir20", 660, {0, {0}}, 0, 0 }, 790 { "eir21", 661, {0, {0}}, 0, 0 }, 791 { "eir22", 662, {0, {0}}, 0, 0 }, 792 { "eir23", 663, {0, {0}}, 0, 0 }, 793 { "eir24", 664, {0, {0}}, 0, 0 }, 794 { "eir25", 665, {0, {0}}, 0, 0 }, 795 { "eir26", 666, {0, {0}}, 0, 0 }, 796 { "eir27", 667, {0, {0}}, 0, 0 }, 797 { "eir28", 668, {0, {0}}, 0, 0 }, 798 { "eir29", 669, {0, {0}}, 0, 0 }, 799 { "eir30", 670, {0, {0}}, 0, 0 }, 800 { "eir31", 671, {0, {0}}, 0, 0 }, 801 { "esfr0", 672, {0, {0}}, 0, 0 }, 802 { "esfr1", 673, {0, {0}}, 0, 0 }, 803 { "sr0", 768, {0, {0}}, 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"edr53", 1653, {0, {0}}, 0, 0 }, 1183 { "edr54", 1654, {0, {0}}, 0, 0 }, 1184 { "edr55", 1655, {0, {0}}, 0, 0 }, 1185 { "edr56", 1656, {0, {0}}, 0, 0 }, 1186 { "edr57", 1657, {0, {0}}, 0, 0 }, 1187 { "edr58", 1658, {0, {0}}, 0, 0 }, 1188 { "edr59", 1659, {0, {0}}, 0, 0 }, 1189 { "edr60", 1660, {0, {0}}, 0, 0 }, 1190 { "edr61", 1661, {0, {0}}, 0, 0 }, 1191 { "edr62", 1662, {0, {0}}, 0, 0 }, 1192 { "edr63", 1663, {0, {0}}, 0, 0 }, 1193 { "iamlr0", 1664, {0, {0}}, 0, 0 }, 1194 { "iamlr1", 1665, {0, {0}}, 0, 0 }, 1195 { "iamlr2", 1666, {0, {0}}, 0, 0 }, 1196 { "iamlr3", 1667, {0, {0}}, 0, 0 }, 1197 { "iamlr4", 1668, {0, {0}}, 0, 0 }, 1198 { "iamlr5", 1669, {0, {0}}, 0, 0 }, 1199 { "iamlr6", 1670, {0, {0}}, 0, 0 }, 1200 { "iamlr7", 1671, {0, {0}}, 0, 0 }, 1201 { "iamlr8", 1672, {0, {0}}, 0, 0 }, 1202 { "iamlr9", 1673, {0, {0}}, 0, 0 }, 1203 { "iamlr10", 1674, {0, {0}}, 0, 0 }, 1204 { "iamlr11", 1675, {0, {0}}, 0, 0 }, 1205 { "iamlr12", 1676, {0, {0}}, 0, 0 }, 1206 { "iamlr13", 1677, {0, {0}}, 0, 0 }, 1207 { "iamlr14", 1678, {0, {0}}, 0, 0 }, 1208 { "iamlr15", 1679, {0, {0}}, 0, 0 }, 1209 { "iamlr16", 1680, {0, {0}}, 0, 0 }, 1210 { "iamlr17", 1681, {0, {0}}, 0, 0 }, 1211 { "iamlr18", 1682, {0, {0}}, 0, 0 }, 1212 { "iamlr19", 1683, {0, {0}}, 0, 0 }, 1213 { "iamlr20", 1684, {0, {0}}, 0, 0 }, 1214 { "iamlr21", 1685, {0, {0}}, 0, 0 }, 1215 { "iamlr22", 1686, {0, {0}}, 0, 0 }, 1216 { "iamlr23", 1687, {0, {0}}, 0, 0 }, 1217 { "iamlr24", 1688, {0, {0}}, 0, 0 }, 1218 { "iamlr25", 1689, {0, {0}}, 0, 0 }, 1219 { "iamlr26", 1690, {0, {0}}, 0, 0 }, 1220 { "iamlr27", 1691, {0, {0}}, 0, 0 }, 1221 { "iamlr28", 1692, {0, {0}}, 0, 0 }, 1222 { "iamlr29", 1693, {0, {0}}, 0, 0 }, 1223 { "iamlr30", 1694, {0, {0}}, 0, 0 }, 1224 { "iamlr31", 1695, {0, {0}}, 0, 0 }, 1225 { "iamlr32", 1696, {0, {0}}, 0, 0 }, 1226 { "iamlr33", 1697, {0, {0}}, 0, 0 }, 1227 { "iamlr34", 1698, {0, {0}}, 0, 0 }, 1228 { "iamlr35", 1699, {0, {0}}, 0, 0 }, 1229 { "iamlr36", 1700, {0, {0}}, 0, 0 }, 1230 { "iamlr37", 1701, {0, {0}}, 0, 0 }, 1231 { "iamlr38", 1702, {0, {0}}, 0, 0 }, 1232 { "iamlr39", 1703, {0, {0}}, 0, 0 }, 1233 { "iamlr40", 1704, {0, {0}}, 0, 0 }, 1234 { "iamlr41", 1705, {0, {0}}, 0, 0 }, 1235 { "iamlr42", 1706, {0, {0}}, 0, 0 }, 1236 { "iamlr43", 1707, {0, {0}}, 0, 0 }, 1237 { "iamlr44", 1708, {0, {0}}, 0, 0 }, 1238 { "iamlr45", 1709, {0, {0}}, 0, 0 }, 1239 { "iamlr46", 1710, {0, {0}}, 0, 0 }, 1240 { "iamlr47", 1711, {0, {0}}, 0, 0 }, 1241 { "iamlr48", 1712, {0, {0}}, 0, 0 }, 1242 { "iamlr49", 1713, {0, {0}}, 0, 0 }, 1243 { "iamlr50", 1714, {0, {0}}, 0, 0 }, 1244 { "iamlr51", 1715, {0, {0}}, 0, 0 }, 1245 { "iamlr52", 1716, {0, {0}}, 0, 0 }, 1246 { "iamlr53", 1717, {0, {0}}, 0, 0 }, 1247 { "iamlr54", 1718, {0, {0}}, 0, 0 }, 1248 { "iamlr55", 1719, {0, {0}}, 0, 0 }, 1249 { "iamlr56", 1720, {0, {0}}, 0, 0 }, 1250 { "iamlr57", 1721, {0, {0}}, 0, 0 }, 1251 { "iamlr58", 1722, {0, {0}}, 0, 0 }, 1252 { "iamlr59", 1723, {0, {0}}, 0, 0 }, 1253 { "iamlr60", 1724, {0, {0}}, 0, 0 }, 1254 { "iamlr61", 1725, {0, {0}}, 0, 0 }, 1255 { "iamlr62", 1726, {0, {0}}, 0, 0 }, 1256 { "iamlr63", 1727, {0, {0}}, 0, 0 }, 1257 { "iampr0", 1728, {0, {0}}, 0, 0 }, 1258 { "iampr1", 1729, {0, {0}}, 0, 0 }, 1259 { "iampr2", 1730, {0, {0}}, 0, 0 }, 1260 { "iampr3", 1731, {0, {0}}, 0, 0 }, 1261 { "iampr4", 1732, {0, {0}}, 0, 0 }, 1262 { "iampr5", 1733, {0, {0}}, 0, 0 }, 1263 { "iampr6", 1734, {0, {0}}, 0, 0 }, 1264 { "iampr7", 1735, {0, {0}}, 0, 0 }, 1265 { "iampr8", 1736, {0, {0}}, 0, 0 }, 1266 { "iampr9", 1737, {0, {0}}, 0, 0 }, 1267 { "iampr10", 1738, {0, {0}}, 0, 0 }, 1268 { "iampr11", 1739, {0, {0}}, 0, 0 }, 1269 { "iampr12", 1740, {0, {0}}, 0, 0 }, 1270 { "iampr13", 1741, {0, {0}}, 0, 0 }, 1271 { "iampr14", 1742, {0, {0}}, 0, 0 }, 1272 { "iampr15", 1743, {0, {0}}, 0, 0 }, 1273 { "iampr16", 1744, {0, {0}}, 0, 0 }, 1274 { "iampr17", 1745, {0, {0}}, 0, 0 }, 1275 { "iampr18", 1746, {0, {0}}, 0, 0 }, 1276 { "iampr19", 1747, {0, {0}}, 0, 0 }, 1277 { "iampr20", 1748, {0, {0}}, 0, 0 }, 1278 { "iampr21", 1749, {0, {0}}, 0, 0 }, 1279 { "iampr22", 1750, {0, {0}}, 0, 0 }, 1280 { "iampr23", 1751, {0, {0}}, 0, 0 }, 1281 { "iampr24", 1752, {0, {0}}, 0, 0 }, 1282 { "iampr25", 1753, {0, {0}}, 0, 0 }, 1283 { "iampr26", 1754, {0, {0}}, 0, 0 }, 1284 { "iampr27", 1755, {0, {0}}, 0, 0 }, 1285 { "iampr28", 1756, {0, {0}}, 0, 0 }, 1286 { "iampr29", 1757, {0, {0}}, 0, 0 }, 1287 { "iampr30", 1758, {0, {0}}, 0, 0 }, 1288 { "iampr31", 1759, {0, {0}}, 0, 0 }, 1289 { "iampr32", 1760, {0, {0}}, 0, 0 }, 1290 { "iampr33", 1761, {0, {0}}, 0, 0 }, 1291 { "iampr34", 1762, {0, {0}}, 0, 0 }, 1292 { "iampr35", 1763, {0, {0}}, 0, 0 }, 1293 { "iampr36", 1764, {0, {0}}, 0, 0 }, 1294 { "iampr37", 1765, {0, {0}}, 0, 0 }, 1295 { "iampr38", 1766, {0, {0}}, 0, 0 }, 1296 { "iampr39", 1767, {0, {0}}, 0, 0 }, 1297 { "iampr40", 1768, {0, {0}}, 0, 0 }, 1298 { "iampr41", 1769, {0, {0}}, 0, 0 }, 1299 { "iampr42", 1770, {0, {0}}, 0, 0 }, 1300 { "iampr43", 1771, {0, {0}}, 0, 0 }, 1301 { "iampr44", 1772, {0, {0}}, 0, 0 }, 1302 { "iampr45", 1773, {0, {0}}, 0, 0 }, 1303 { "iampr46", 1774, {0, {0}}, 0, 0 }, 1304 { "iampr47", 1775, {0, {0}}, 0, 0 }, 1305 { "iampr48", 1776, {0, {0}}, 0, 0 }, 1306 { "iampr49", 1777, {0, {0}}, 0, 0 }, 1307 { "iampr50", 1778, {0, {0}}, 0, 0 }, 1308 { "iampr51", 1779, {0, {0}}, 0, 0 }, 1309 { "iampr52", 1780, {0, {0}}, 0, 0 }, 1310 { "iampr53", 1781, {0, {0}}, 0, 0 }, 1311 { "iampr54", 1782, {0, {0}}, 0, 0 }, 1312 { "iampr55", 1783, {0, {0}}, 0, 0 }, 1313 { "iampr56", 1784, {0, {0}}, 0, 0 }, 1314 { "iampr57", 1785, {0, {0}}, 0, 0 }, 1315 { "iampr58", 1786, {0, {0}}, 0, 0 }, 1316 { "iampr59", 1787, {0, {0}}, 0, 0 }, 1317 { "iampr60", 1788, {0, {0}}, 0, 0 }, 1318 { "iampr61", 1789, {0, {0}}, 0, 0 }, 1319 { "iampr62", 1790, {0, {0}}, 0, 0 }, 1320 { "iampr63", 1791, {0, {0}}, 0, 0 }, 1321 { "damlr0", 1792, {0, {0}}, 0, 0 }, 1322 { "damlr1", 1793, {0, {0}}, 0, 0 }, 1323 { "damlr2", 1794, {0, {0}}, 0, 0 }, 1324 { "damlr3", 1795, {0, {0}}, 0, 0 }, 1325 { "damlr4", 1796, {0, {0}}, 0, 0 }, 1326 { "damlr5", 1797, {0, {0}}, 0, 0 }, 1327 { "damlr6", 1798, {0, {0}}, 0, 0 }, 1328 { "damlr7", 1799, {0, {0}}, 0, 0 }, 1329 { "damlr8", 1800, {0, {0}}, 0, 0 }, 1330 { "damlr9", 1801, {0, {0}}, 0, 0 }, 1331 { "damlr10", 1802, {0, {0}}, 0, 0 }, 1332 { "damlr11", 1803, {0, {0}}, 0, 0 }, 1333 { "damlr12", 1804, {0, {0}}, 0, 0 }, 1334 { "damlr13", 1805, {0, {0}}, 0, 0 }, 1335 { "damlr14", 1806, {0, {0}}, 0, 0 }, 1336 { "damlr15", 1807, {0, {0}}, 0, 0 }, 1337 { "damlr16", 1808, {0, {0}}, 0, 0 }, 1338 { "damlr17", 1809, {0, {0}}, 0, 0 }, 1339 { "damlr18", 1810, {0, {0}}, 0, 0 }, 1340 { "damlr19", 1811, {0, {0}}, 0, 0 }, 1341 { "damlr20", 1812, {0, {0}}, 0, 0 }, 1342 { "damlr21", 1813, {0, {0}}, 0, 0 }, 1343 { "damlr22", 1814, {0, {0}}, 0, 0 }, 1344 { "damlr23", 1815, {0, {0}}, 0, 0 }, 1345 { "damlr24", 1816, {0, {0}}, 0, 0 }, 1346 { "damlr25", 1817, {0, {0}}, 0, 0 }, 1347 { "damlr26", 1818, {0, {0}}, 0, 0 }, 1348 { "damlr27", 1819, {0, {0}}, 0, 0 }, 1349 { "damlr28", 1820, {0, {0}}, 0, 0 }, 1350 { "damlr29", 1821, {0, {0}}, 0, 0 }, 1351 { "damlr30", 1822, {0, {0}}, 0, 0 }, 1352 { "damlr31", 1823, {0, {0}}, 0, 0 }, 1353 { "damlr32", 1824, {0, {0}}, 0, 0 }, 1354 { "damlr33", 1825, {0, {0}}, 0, 0 }, 1355 { "damlr34", 1826, {0, {0}}, 0, 0 }, 1356 { "damlr35", 1827, {0, {0}}, 0, 0 }, 1357 { "damlr36", 1828, {0, {0}}, 0, 0 }, 1358 { "damlr37", 1829, {0, {0}}, 0, 0 }, 1359 { "damlr38", 1830, {0, {0}}, 0, 0 }, 1360 { "damlr39", 1831, {0, {0}}, 0, 0 }, 1361 { "damlr40", 1832, {0, {0}}, 0, 0 }, 1362 { "damlr41", 1833, {0, {0}}, 0, 0 }, 1363 { "damlr42", 1834, {0, {0}}, 0, 0 }, 1364 { "damlr43", 1835, {0, {0}}, 0, 0 }, 1365 { "damlr44", 1836, {0, {0}}, 0, 0 }, 1366 { "damlr45", 1837, {0, {0}}, 0, 0 }, 1367 { "damlr46", 1838, {0, {0}}, 0, 0 }, 1368 { "damlr47", 1839, {0, {0}}, 0, 0 }, 1369 { "damlr48", 1840, {0, {0}}, 0, 0 }, 1370 { "damlr49", 1841, {0, {0}}, 0, 0 }, 1371 { "damlr50", 1842, {0, {0}}, 0, 0 }, 1372 { "damlr51", 1843, {0, {0}}, 0, 0 }, 1373 { "damlr52", 1844, {0, {0}}, 0, 0 }, 1374 { "damlr53", 1845, {0, {0}}, 0, 0 }, 1375 { "damlr54", 1846, {0, {0}}, 0, 0 }, 1376 { "damlr55", 1847, {0, {0}}, 0, 0 }, 1377 { "damlr56", 1848, {0, {0}}, 0, 0 }, 1378 { "damlr57", 1849, {0, {0}}, 0, 0 }, 1379 { "damlr58", 1850, {0, {0}}, 0, 0 }, 1380 { "damlr59", 1851, {0, {0}}, 0, 0 }, 1381 { "damlr60", 1852, {0, {0}}, 0, 0 }, 1382 { "damlr61", 1853, {0, {0}}, 0, 0 }, 1383 { "damlr62", 1854, {0, {0}}, 0, 0 }, 1384 { "damlr63", 1855, {0, {0}}, 0, 0 }, 1385 { "dampr0", 1856, {0, {0}}, 0, 0 }, 1386 { "dampr1", 1857, {0, {0}}, 0, 0 }, 1387 { "dampr2", 1858, {0, {0}}, 0, 0 }, 1388 { "dampr3", 1859, {0, {0}}, 0, 0 }, 1389 { "dampr4", 1860, {0, {0}}, 0, 0 }, 1390 { "dampr5", 1861, {0, {0}}, 0, 0 }, 1391 { "dampr6", 1862, {0, {0}}, 0, 0 }, 1392 { "dampr7", 1863, {0, {0}}, 0, 0 }, 1393 { "dampr8", 1864, {0, {0}}, 0, 0 }, 1394 { "dampr9", 1865, {0, {0}}, 0, 0 }, 1395 { "dampr10", 1866, {0, {0}}, 0, 0 }, 1396 { "dampr11", 1867, {0, {0}}, 0, 0 }, 1397 { "dampr12", 1868, {0, {0}}, 0, 0 }, 1398 { "dampr13", 1869, {0, {0}}, 0, 0 }, 1399 { "dampr14", 1870, {0, {0}}, 0, 0 }, 1400 { "dampr15", 1871, {0, {0}}, 0, 0 }, 1401 { "dampr16", 1872, {0, {0}}, 0, 0 }, 1402 { "dampr17", 1873, {0, {0}}, 0, 0 }, 1403 { "dampr18", 1874, {0, {0}}, 0, 0 }, 1404 { "dampr19", 1875, {0, {0}}, 0, 0 }, 1405 { "dampr20", 1876, {0, {0}}, 0, 0 }, 1406 { "dampr21", 1877, {0, {0}}, 0, 0 }, 1407 { "dampr22", 1878, {0, {0}}, 0, 0 }, 1408 { "dampr23", 1879, {0, {0}}, 0, 0 }, 1409 { "dampr24", 1880, {0, {0}}, 0, 0 }, 1410 { "dampr25", 1881, {0, {0}}, 0, 0 }, 1411 { "dampr26", 1882, {0, {0}}, 0, 0 }, 1412 { "dampr27", 1883, {0, {0}}, 0, 0 }, 1413 { "dampr28", 1884, {0, {0}}, 0, 0 }, 1414 { "dampr29", 1885, {0, {0}}, 0, 0 }, 1415 { "dampr30", 1886, {0, {0}}, 0, 0 }, 1416 { "dampr31", 1887, {0, {0}}, 0, 0 }, 1417 { "dampr32", 1888, {0, {0}}, 0, 0 }, 1418 { "dampr33", 1889, {0, {0}}, 0, 0 }, 1419 { "dampr34", 1890, {0, {0}}, 0, 0 }, 1420 { "dampr35", 1891, {0, {0}}, 0, 0 }, 1421 { "dampr36", 1892, {0, {0}}, 0, 0 }, 1422 { "dampr37", 1893, {0, {0}}, 0, 0 }, 1423 { "dampr38", 1894, {0, {0}}, 0, 0 }, 1424 { "dampr39", 1895, {0, {0}}, 0, 0 }, 1425 { "dampr40", 1896, {0, {0}}, 0, 0 }, 1426 { "dampr41", 1897, {0, {0}}, 0, 0 }, 1427 { "dampr42", 1898, {0, {0}}, 0, 0 }, 1428 { "dampr43", 1899, {0, {0}}, 0, 0 }, 1429 { "dampr44", 1900, {0, {0}}, 0, 0 }, 1430 { "dampr45", 1901, {0, {0}}, 0, 0 }, 1431 { "dampr46", 1902, {0, {0}}, 0, 0 }, 1432 { "dampr47", 1903, {0, {0}}, 0, 0 }, 1433 { "dampr48", 1904, {0, {0}}, 0, 0 }, 1434 { "dampr49", 1905, {0, {0}}, 0, 0 }, 1435 { "dampr50", 1906, {0, {0}}, 0, 0 }, 1436 { "dampr51", 1907, {0, {0}}, 0, 0 }, 1437 { "dampr52", 1908, {0, {0}}, 0, 0 }, 1438 { "dampr53", 1909, {0, {0}}, 0, 0 }, 1439 { "dampr54", 1910, {0, {0}}, 0, 0 }, 1440 { "dampr55", 1911, {0, {0}}, 0, 0 }, 1441 { "dampr56", 1912, {0, {0}}, 0, 0 }, 1442 { "dampr57", 1913, {0, {0}}, 0, 0 }, 1443 { "dampr58", 1914, {0, {0}}, 0, 0 }, 1444 { "dampr59", 1915, {0, {0}}, 0, 0 }, 1445 { "dampr60", 1916, {0, {0}}, 0, 0 }, 1446 { "dampr61", 1917, {0, {0}}, 0, 0 }, 1447 { "dampr62", 1918, {0, {0}}, 0, 0 }, 1448 { "dampr63", 1919, {0, {0}}, 0, 0 }, 1449 { "amcr", 1920, {0, {0}}, 0, 0 }, 1450 { "stbar", 1921, {0, {0}}, 0, 0 }, 1451 { "mmcr", 1922, {0, {0}}, 0, 0 }, 1452 { "dcr", 2048, {0, {0}}, 0, 0 }, 1453 { "brr", 2049, {0, {0}}, 0, 0 }, 1454 { "nmar", 2050, {0, {0}}, 0, 0 }, 1455 { "ibar0", 2052, {0, {0}}, 0, 0 }, 1456 { "ibar1", 2053, {0, {0}}, 0, 0 }, 1457 { "ibar2", 2054, {0, {0}}, 0, 0 }, 1458 { "ibar3", 2055, {0, {0}}, 0, 0 }, 1459 { "dbar0", 2056, {0, {0}}, 0, 0 }, 1460 { "dbar1", 2057, {0, {0}}, 0, 0 }, 1461 { "dbar2", 2058, {0, {0}}, 0, 0 }, 1462 { "dbar3", 2059, {0, {0}}, 0, 0 }, 1463 { "dbdr00", 2060, {0, {0}}, 0, 0 }, 1464 { "dbdr01", 2061, {0, {0}}, 0, 0 }, 1465 { "dbdr02", 2062, {0, {0}}, 0, 0 }, 1466 { "dbdr03", 2063, {0, {0}}, 0, 0 }, 1467 { "dbdr10", 2064, {0, {0}}, 0, 0 }, 1468 { "dbdr11", 2065, {0, {0}}, 0, 0 }, 1469 { "dbdr12", 2066, {0, {0}}, 0, 0 }, 1470 { "dbdr13", 2067, {0, {0}}, 0, 0 }, 1471 { "dbdr20", 2068, {0, {0}}, 0, 0 }, 1472 { "dbdr21", 2069, {0, {0}}, 0, 0 }, 1473 { "dbdr22", 2070, {0, {0}}, 0, 0 }, 1474 { "dbdr23", 2071, {0, {0}}, 0, 0 }, 1475 { "dbdr30", 2072, {0, {0}}, 0, 0 }, 1476 { "dbdr31", 2073, {0, {0}}, 0, 0 }, 1477 { "dbdr32", 2074, {0, {0}}, 0, 0 }, 1478 { "dbdr33", 2075, {0, {0}}, 0, 0 }, 1479 { "dbmr00", 2076, {0, {0}}, 0, 0 }, 1480 { "dbmr01", 2077, {0, {0}}, 0, 0 }, 1481 { "dbmr02", 2078, {0, {0}}, 0, 0 }, 1482 { "dbmr03", 2079, {0, {0}}, 0, 0 }, 1483 { "dbmr10", 2080, {0, {0}}, 0, 0 }, 1484 { "dbmr11", 2081, {0, {0}}, 0, 0 }, 1485 { "dbmr12", 2082, {0, {0}}, 0, 0 }, 1486 { "dbmr13", 2083, {0, {0}}, 0, 0 }, 1487 { "dbmr20", 2084, {0, {0}}, 0, 0 }, 1488 { "dbmr21", 2085, {0, {0}}, 0, 0 }, 1489 { "dbmr22", 2086, {0, {0}}, 0, 0 }, 1490 { "dbmr23", 2087, {0, {0}}, 0, 0 }, 1491 { "dbmr30", 2088, {0, {0}}, 0, 0 }, 1492 { "dbmr31", 2089, {0, {0}}, 0, 0 }, 1493 { "dbmr32", 2090, {0, {0}}, 0, 0 }, 1494 { "dbmr33", 2091, {0, {0}}, 0, 0 }, 1495 { "cpcfr", 2092, {0, {0}}, 0, 0 }, 1496 { "cpcr", 2093, {0, {0}}, 0, 0 }, 1497 { "cpsr", 2094, {0, {0}}, 0, 0 }, 1498 { "cpesr0", 2096, {0, {0}}, 0, 0 }, 1499 { "cpesr1", 2097, {0, {0}}, 0, 0 }, 1500 { "cpemr0", 2098, {0, {0}}, 0, 0 }, 1501 { "cpemr1", 2099, {0, {0}}, 0, 0 }, 1502 { "ihsr8", 3848, {0, {0}}, 0, 0 } 1503 }; 1504 1505 CGEN_KEYWORD frv_cgen_opval_spr_names = 1506 { 1507 & frv_cgen_opval_spr_names_entries[0], 1508 1007, 1509 0, 0, 0, 0, "" 1510 }; 1511 1512 static CGEN_KEYWORD_ENTRY frv_cgen_opval_accg_names_entries[] = 1513 { 1514 { "accg0", 0, {0, {0}}, 0, 0 }, 1515 { "accg1", 1, {0, {0}}, 0, 0 }, 1516 { "accg2", 2, {0, {0}}, 0, 0 }, 1517 { "accg3", 3, {0, {0}}, 0, 0 }, 1518 { "accg4", 4, {0, {0}}, 0, 0 }, 1519 { "accg5", 5, {0, {0}}, 0, 0 }, 1520 { "accg6", 6, {0, {0}}, 0, 0 }, 1521 { "accg7", 7, {0, {0}}, 0, 0 }, 1522 { "accg8", 8, {0, {0}}, 0, 0 }, 1523 { "accg9", 9, {0, {0}}, 0, 0 }, 1524 { "accg10", 10, {0, {0}}, 0, 0 }, 1525 { "accg11", 11, {0, {0}}, 0, 0 }, 1526 { "accg12", 12, {0, {0}}, 0, 0 }, 1527 { "accg13", 13, {0, {0}}, 0, 0 }, 1528 { "accg14", 14, {0, {0}}, 0, 0 }, 1529 { "accg15", 15, {0, {0}}, 0, 0 }, 1530 { "accg16", 16, {0, {0}}, 0, 0 }, 1531 { "accg17", 17, {0, {0}}, 0, 0 }, 1532 { "accg18", 18, {0, {0}}, 0, 0 }, 1533 { "accg19", 19, {0, {0}}, 0, 0 }, 1534 { "accg20", 20, {0, {0}}, 0, 0 }, 1535 { "accg21", 21, {0, {0}}, 0, 0 }, 1536 { "accg22", 22, {0, {0}}, 0, 0 }, 1537 { "accg23", 23, {0, {0}}, 0, 0 }, 1538 { "accg24", 24, {0, {0}}, 0, 0 }, 1539 { "accg25", 25, {0, {0}}, 0, 0 }, 1540 { "accg26", 26, {0, {0}}, 0, 0 }, 1541 { "accg27", 27, {0, {0}}, 0, 0 }, 1542 { "accg28", 28, {0, {0}}, 0, 0 }, 1543 { "accg29", 29, {0, {0}}, 0, 0 }, 1544 { "accg30", 30, {0, {0}}, 0, 0 }, 1545 { "accg31", 31, {0, {0}}, 0, 0 }, 1546 { "accg32", 32, {0, {0}}, 0, 0 }, 1547 { "accg33", 33, {0, {0}}, 0, 0 }, 1548 { "accg34", 34, {0, {0}}, 0, 0 }, 1549 { "accg35", 35, {0, {0}}, 0, 0 }, 1550 { "accg36", 36, {0, {0}}, 0, 0 }, 1551 { "accg37", 37, {0, {0}}, 0, 0 }, 1552 { "accg38", 38, {0, {0}}, 0, 0 }, 1553 { "accg39", 39, {0, {0}}, 0, 0 }, 1554 { "accg40", 40, {0, {0}}, 0, 0 }, 1555 { "accg41", 41, {0, {0}}, 0, 0 }, 1556 { "accg42", 42, {0, {0}}, 0, 0 }, 1557 { "accg43", 43, {0, {0}}, 0, 0 }, 1558 { "accg44", 44, {0, {0}}, 0, 0 }, 1559 { "accg45", 45, {0, {0}}, 0, 0 }, 1560 { "accg46", 46, {0, {0}}, 0, 0 }, 1561 { "accg47", 47, {0, {0}}, 0, 0 }, 1562 { "accg48", 48, {0, {0}}, 0, 0 }, 1563 { "accg49", 49, {0, {0}}, 0, 0 }, 1564 { "accg50", 50, {0, {0}}, 0, 0 }, 1565 { "accg51", 51, {0, {0}}, 0, 0 }, 1566 { "accg52", 52, {0, {0}}, 0, 0 }, 1567 { "accg53", 53, {0, {0}}, 0, 0 }, 1568 { "accg54", 54, {0, {0}}, 0, 0 }, 1569 { "accg55", 55, {0, {0}}, 0, 0 }, 1570 { "accg56", 56, {0, {0}}, 0, 0 }, 1571 { "accg57", 57, {0, {0}}, 0, 0 }, 1572 { "accg58", 58, {0, {0}}, 0, 0 }, 1573 { "accg59", 59, {0, {0}}, 0, 0 }, 1574 { "accg60", 60, {0, {0}}, 0, 0 }, 1575 { "accg61", 61, {0, {0}}, 0, 0 }, 1576 { "accg62", 62, {0, {0}}, 0, 0 }, 1577 { "accg63", 63, {0, {0}}, 0, 0 } 1578 }; 1579 1580 CGEN_KEYWORD frv_cgen_opval_accg_names = 1581 { 1582 & frv_cgen_opval_accg_names_entries[0], 1583 64, 1584 0, 0, 0, 0, "" 1585 }; 1586 1587 static CGEN_KEYWORD_ENTRY frv_cgen_opval_acc_names_entries[] = 1588 { 1589 { "acc0", 0, {0, {0}}, 0, 0 }, 1590 { "acc1", 1, {0, {0}}, 0, 0 }, 1591 { "acc2", 2, {0, {0}}, 0, 0 }, 1592 { "acc3", 3, {0, {0}}, 0, 0 }, 1593 { "acc4", 4, {0, {0}}, 0, 0 }, 1594 { "acc5", 5, {0, {0}}, 0, 0 }, 1595 { "acc6", 6, {0, {0}}, 0, 0 }, 1596 { "acc7", 7, {0, {0}}, 0, 0 }, 1597 { "acc8", 8, {0, {0}}, 0, 0 }, 1598 { "acc9", 9, {0, {0}}, 0, 0 }, 1599 { "acc10", 10, {0, {0}}, 0, 0 }, 1600 { "acc11", 11, {0, {0}}, 0, 0 }, 1601 { "acc12", 12, {0, {0}}, 0, 0 }, 1602 { "acc13", 13, {0, {0}}, 0, 0 }, 1603 { "acc14", 14, {0, {0}}, 0, 0 }, 1604 { "acc15", 15, {0, {0}}, 0, 0 }, 1605 { "acc16", 16, {0, {0}}, 0, 0 }, 1606 { "acc17", 17, {0, {0}}, 0, 0 }, 1607 { "acc18", 18, {0, {0}}, 0, 0 }, 1608 { "acc19", 19, {0, {0}}, 0, 0 }, 1609 { "acc20", 20, {0, {0}}, 0, 0 }, 1610 { "acc21", 21, {0, {0}}, 0, 0 }, 1611 { "acc22", 22, {0, {0}}, 0, 0 }, 1612 { "acc23", 23, {0, {0}}, 0, 0 }, 1613 { "acc24", 24, {0, {0}}, 0, 0 }, 1614 { "acc25", 25, {0, {0}}, 0, 0 }, 1615 { "acc26", 26, {0, {0}}, 0, 0 }, 1616 { "acc27", 27, {0, {0}}, 0, 0 }, 1617 { "acc28", 28, {0, {0}}, 0, 0 }, 1618 { "acc29", 29, {0, {0}}, 0, 0 }, 1619 { "acc30", 30, {0, {0}}, 0, 0 }, 1620 { "acc31", 31, {0, {0}}, 0, 0 }, 1621 { "acc32", 32, {0, {0}}, 0, 0 }, 1622 { "acc33", 33, {0, {0}}, 0, 0 }, 1623 { "acc34", 34, {0, {0}}, 0, 0 }, 1624 { "acc35", 35, {0, {0}}, 0, 0 }, 1625 { "acc36", 36, {0, {0}}, 0, 0 }, 1626 { "acc37", 37, {0, {0}}, 0, 0 }, 1627 { "acc38", 38, {0, {0}}, 0, 0 }, 1628 { "acc39", 39, {0, {0}}, 0, 0 }, 1629 { "acc40", 40, {0, {0}}, 0, 0 }, 1630 { "acc41", 41, {0, {0}}, 0, 0 }, 1631 { "acc42", 42, {0, {0}}, 0, 0 }, 1632 { "acc43", 43, {0, {0}}, 0, 0 }, 1633 { "acc44", 44, {0, {0}}, 0, 0 }, 1634 { "acc45", 45, {0, {0}}, 0, 0 }, 1635 { "acc46", 46, {0, {0}}, 0, 0 }, 1636 { "acc47", 47, {0, {0}}, 0, 0 }, 1637 { "acc48", 48, {0, {0}}, 0, 0 }, 1638 { "acc49", 49, {0, {0}}, 0, 0 }, 1639 { "acc50", 50, {0, {0}}, 0, 0 }, 1640 { "acc51", 51, {0, {0}}, 0, 0 }, 1641 { "acc52", 52, {0, {0}}, 0, 0 }, 1642 { "acc53", 53, {0, {0}}, 0, 0 }, 1643 { "acc54", 54, {0, {0}}, 0, 0 }, 1644 { "acc55", 55, {0, {0}}, 0, 0 }, 1645 { "acc56", 56, {0, {0}}, 0, 0 }, 1646 { "acc57", 57, {0, {0}}, 0, 0 }, 1647 { "acc58", 58, {0, {0}}, 0, 0 }, 1648 { "acc59", 59, {0, {0}}, 0, 0 }, 1649 { "acc60", 60, {0, {0}}, 0, 0 }, 1650 { "acc61", 61, {0, {0}}, 0, 0 }, 1651 { "acc62", 62, {0, {0}}, 0, 0 }, 1652 { "acc63", 63, {0, {0}}, 0, 0 } 1653 }; 1654 1655 CGEN_KEYWORD frv_cgen_opval_acc_names = 1656 { 1657 & frv_cgen_opval_acc_names_entries[0], 1658 64, 1659 0, 0, 0, 0, "" 1660 }; 1661 1662 static CGEN_KEYWORD_ENTRY frv_cgen_opval_iacc0_names_entries[] = 1663 { 1664 { "iacc0", 0, {0, {0}}, 0, 0 } 1665 }; 1666 1667 CGEN_KEYWORD frv_cgen_opval_iacc0_names = 1668 { 1669 & frv_cgen_opval_iacc0_names_entries[0], 1670 1, 1671 0, 0, 0, 0, "" 1672 }; 1673 1674 static CGEN_KEYWORD_ENTRY frv_cgen_opval_iccr_names_entries[] = 1675 { 1676 { "icc0", 0, {0, {0}}, 0, 0 }, 1677 { "icc1", 1, {0, {0}}, 0, 0 }, 1678 { "icc2", 2, {0, {0}}, 0, 0 }, 1679 { "icc3", 3, {0, {0}}, 0, 0 } 1680 }; 1681 1682 CGEN_KEYWORD frv_cgen_opval_iccr_names = 1683 { 1684 & frv_cgen_opval_iccr_names_entries[0], 1685 4, 1686 0, 0, 0, 0, "" 1687 }; 1688 1689 static CGEN_KEYWORD_ENTRY frv_cgen_opval_fccr_names_entries[] = 1690 { 1691 { "fcc0", 0, {0, {0}}, 0, 0 }, 1692 { "fcc1", 1, {0, {0}}, 0, 0 }, 1693 { "fcc2", 2, {0, {0}}, 0, 0 }, 1694 { "fcc3", 3, {0, {0}}, 0, 0 } 1695 }; 1696 1697 CGEN_KEYWORD frv_cgen_opval_fccr_names = 1698 { 1699 & frv_cgen_opval_fccr_names_entries[0], 1700 4, 1701 0, 0, 0, 0, "" 1702 }; 1703 1704 static CGEN_KEYWORD_ENTRY frv_cgen_opval_cccr_names_entries[] = 1705 { 1706 { "cc0", 0, {0, {0}}, 0, 0 }, 1707 { "cc1", 1, {0, {0}}, 0, 0 }, 1708 { "cc2", 2, {0, {0}}, 0, 0 }, 1709 { "cc3", 3, {0, {0}}, 0, 0 }, 1710 { "cc4", 4, {0, {0}}, 0, 0 }, 1711 { "cc5", 5, {0, {0}}, 0, 0 }, 1712 { "cc6", 6, {0, {0}}, 0, 0 }, 1713 { "cc7", 7, {0, {0}}, 0, 0 } 1714 }; 1715 1716 CGEN_KEYWORD frv_cgen_opval_cccr_names = 1717 { 1718 & frv_cgen_opval_cccr_names_entries[0], 1719 8, 1720 0, 0, 0, 0, "" 1721 }; 1722 1723 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_pack_entries[] = 1724 { 1725 { "", 1, {0, {0}}, 0, 0 }, 1726 { ".p", 0, {0, {0}}, 0, 0 }, 1727 { ".P", 0, {0, {0}}, 0, 0 } 1728 }; 1729 1730 CGEN_KEYWORD frv_cgen_opval_h_pack = 1731 { 1732 & frv_cgen_opval_h_pack_entries[0], 1733 3, 1734 0, 0, 0, 0, "" 1735 }; 1736 1737 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_taken_entries[] = 1738 { 1739 { "", 2, {0, {0}}, 0, 0 }, 1740 { "", 0, {0, {0}}, 0, 0 }, 1741 { "", 1, {0, {0}}, 0, 0 }, 1742 { "", 3, {0, {0}}, 0, 0 } 1743 }; 1744 1745 CGEN_KEYWORD frv_cgen_opval_h_hint_taken = 1746 { 1747 & frv_cgen_opval_h_hint_taken_entries[0], 1748 4, 1749 0, 0, 0, 0, "" 1750 }; 1751 1752 static CGEN_KEYWORD_ENTRY frv_cgen_opval_h_hint_not_taken_entries[] = 1753 { 1754 { "", 0, {0, {0}}, 0, 0 }, 1755 { "", 1, {0, {0}}, 0, 0 }, 1756 { "", 2, {0, {0}}, 0, 0 }, 1757 { "", 3, {0, {0}}, 0, 0 } 1758 }; 1759 1760 CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken = 1761 { 1762 & frv_cgen_opval_h_hint_not_taken_entries[0], 1763 4, 1764 0, 0, 0, 0, "" 1765 }; 1766 1767 1768 /* The hardware table. */ 1769 1770 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) 1771 #define A(a) (1 << CGEN_HW_##a) 1772 #else 1773 #define A(a) (1 << CGEN_HW_/**/a) 1774 #endif 1775 1776 const CGEN_HW_ENTRY frv_cgen_hw_table[] = 1777 { 1778 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1779 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1780 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1781 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1782 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1783 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } }, 1784 { "h-psr_imple", HW_H_PSR_IMPLE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1785 { "h-psr_ver", HW_H_PSR_VER, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1786 { "h-psr_ice", HW_H_PSR_ICE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1787 { "h-psr_nem", HW_H_PSR_NEM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1788 { "h-psr_cm", HW_H_PSR_CM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1789 { "h-psr_be", HW_H_PSR_BE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1790 { "h-psr_esr", HW_H_PSR_ESR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1791 { "h-psr_ef", HW_H_PSR_EF, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1792 { "h-psr_em", HW_H_PSR_EM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1793 { "h-psr_pil", HW_H_PSR_PIL, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1794 { "h-psr_ps", HW_H_PSR_PS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1795 { "h-psr_et", HW_H_PSR_ET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1796 { "h-psr_s", HW_H_PSR_S, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1797 { "h-tbr_tba", HW_H_TBR_TBA, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1798 { "h-tbr_tt", HW_H_TBR_TT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1799 { "h-bpsr_bs", HW_H_BPSR_BS, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1800 { "h-bpsr_bet", HW_H_BPSR_BET, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } }, 1801 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, 1802 { "h-gr_double", HW_H_GR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, 1803 { "h-gr_hi", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, 1804 { "h-gr_lo", HW_H_GR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, 1805 { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, 1806 { "h-fr_double", HW_H_FR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, 1807 { "h-fr_int", HW_H_FR_INT, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, 1808 { "h-fr_hi", HW_H_FR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, 1809 { "h-fr_lo", HW_H_FR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, 1810 { "h-fr_0", HW_H_FR_0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, 1811 { "h-fr_1", HW_H_FR_1, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, 1812 { "h-fr_2", HW_H_FR_2, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, 1813 { "h-fr_3", HW_H_FR_3, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, 1814 { "h-cpr", HW_H_CPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(PROFILE), { (1<<MACH_FRV) } } }, 1815 { "h-cpr_double", HW_H_CPR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cpr_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FRV) } } }, 1816 { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_spr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, 1817 { "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, 1818 { "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, 1819 { "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } }, 1820 { "h-iacc0", HW_H_IACC0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iacc0_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FR400) } } }, 1821 { "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, 1822 { "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, 1823 { "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } }, 1824 { "h-pack", HW_H_PACK, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_pack, { 0, { (1<<MACH_BASE) } } }, 1825 { "h-hint-taken", HW_H_HINT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_taken, { 0, { (1<<MACH_BASE) } } }, 1826 { "h-hint-not-taken", HW_H_HINT_NOT_TAKEN, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_h_hint_not_taken, { 0, { (1<<MACH_BASE) } } }, 1827 { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} } 1828 }; 1829 1830 #undef A 1831 1832 1833 /* The instruction field table. */ 1834 1835 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) 1836 #define A(a) (1 << CGEN_IFLD_##a) 1837 #else 1838 #define A(a) (1 << CGEN_IFLD_/**/a) 1839 #endif 1840 1841 const CGEN_IFLD frv_cgen_ifld_table[] = 1842 { 1843 { FRV_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, 1844 { FRV_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } }, 1845 { FRV_F_PACK, "f-pack", 0, 32, 31, 1, { 0, { (1<<MACH_BASE) } } }, 1846 { FRV_F_OP, "f-op", 0, 32, 24, 7, { 0, { (1<<MACH_BASE) } } }, 1847 { FRV_F_OPE1, "f-ope1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } } }, 1848 { FRV_F_OPE2, "f-ope2", 0, 32, 9, 4, { 0, { (1<<MACH_BASE) } } }, 1849 { FRV_F_OPE3, "f-ope3", 0, 32, 15, 3, { 0, { (1<<MACH_BASE) } } }, 1850 { FRV_F_OPE4, "f-ope4", 0, 32, 7, 2, { 0, { (1<<MACH_BASE) } } }, 1851 { FRV_F_GRI, "f-GRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, 1852 { FRV_F_GRJ, "f-GRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, 1853 { FRV_F_GRK, "f-GRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, 1854 { FRV_F_FRI, "f-FRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, 1855 { FRV_F_FRJ, "f-FRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, 1856 { FRV_F_FRK, "f-FRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, 1857 { FRV_F_CPRI, "f-CPRi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, 1858 { FRV_F_CPRJ, "f-CPRj", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, 1859 { FRV_F_CPRK, "f-CPRk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, 1860 { FRV_F_ACCGI, "f-ACCGi", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, 1861 { FRV_F_ACCGK, "f-ACCGk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, 1862 { FRV_F_ACC40SI, "f-ACC40Si", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, 1863 { FRV_F_ACC40UI, "f-ACC40Ui", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, 1864 { FRV_F_ACC40SK, "f-ACC40Sk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, 1865 { FRV_F_ACC40UK, "f-ACC40Uk", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, 1866 { FRV_F_CRI, "f-CRi", 0, 32, 14, 3, { 0, { (1<<MACH_BASE) } } }, 1867 { FRV_F_CRJ, "f-CRj", 0, 32, 2, 3, { 0, { (1<<MACH_BASE) } } }, 1868 { FRV_F_CRK, "f-CRk", 0, 32, 27, 3, { 0, { (1<<MACH_BASE) } } }, 1869 { FRV_F_CCI, "f-CCi", 0, 32, 11, 3, { 0, { (1<<MACH_BASE) } } }, 1870 { FRV_F_CRJ_INT, "f-CRj_int", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } }, 1871 { FRV_F_CRJ_FLOAT, "f-CRj_float", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } }, 1872 { FRV_F_ICCI_1, "f-ICCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } } }, 1873 { FRV_F_ICCI_2, "f-ICCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } }, 1874 { FRV_F_ICCI_3, "f-ICCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } } }, 1875 { FRV_F_FCCI_1, "f-FCCi_1", 0, 32, 11, 2, { 0, { (1<<MACH_BASE) } } }, 1876 { FRV_F_FCCI_2, "f-FCCi_2", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } }, 1877 { FRV_F_FCCI_3, "f-FCCi_3", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } } }, 1878 { FRV_F_FCCK, "f-FCCk", 0, 32, 26, 2, { 0, { (1<<MACH_BASE) } } }, 1879 { FRV_F_EIR, "f-eir", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, 1880 { FRV_F_S10, "f-s10", 0, 32, 9, 10, { 0, { (1<<MACH_BASE) } } }, 1881 { FRV_F_S12, "f-s12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } } }, 1882 { FRV_F_D12, "f-d12", 0, 32, 11, 12, { 0, { (1<<MACH_BASE) } } }, 1883 { FRV_F_U16, "f-u16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } }, 1884 { FRV_F_S16, "f-s16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } }, 1885 { FRV_F_S6, "f-s6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, 1886 { FRV_F_S6_1, "f-s6_1", 0, 32, 11, 6, { 0, { (1<<MACH_BASE) } } }, 1887 { FRV_F_U6, "f-u6", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, 1888 { FRV_F_S5, "f-s5", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } } }, 1889 { FRV_F_U12_H, "f-u12-h", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, 1890 { FRV_F_U12_L, "f-u12-l", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } }, 1891 { FRV_F_U12, "f-u12", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, 1892 { FRV_F_INT_CC, "f-int-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } } }, 1893 { FRV_F_FLT_CC, "f-flt-cc", 0, 32, 30, 4, { 0, { (1<<MACH_BASE) } } }, 1894 { FRV_F_COND, "f-cond", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } } }, 1895 { FRV_F_CCOND, "f-ccond", 0, 32, 12, 1, { 0, { (1<<MACH_BASE) } } }, 1896 { FRV_F_HINT, "f-hint", 0, 32, 17, 2, { 0, { (1<<MACH_BASE) } } }, 1897 { FRV_F_LI, "f-LI", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } }, 1898 { FRV_F_LOCK, "f-lock", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } }, 1899 { FRV_F_DEBUG, "f-debug", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } }, 1900 { FRV_F_A, "f-A", 0, 32, 17, 1, { 0, { (1<<MACH_BASE) } } }, 1901 { FRV_F_AE, "f-ae", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } }, 1902 { FRV_F_SPR_H, "f-spr-h", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, 1903 { FRV_F_SPR_L, "f-spr-l", 0, 32, 17, 6, { 0, { (1<<MACH_BASE) } } }, 1904 { FRV_F_SPR, "f-spr", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, 1905 { FRV_F_LABEL16, "f-label16", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, 1906 { FRV_F_LABELH6, "f-labelH6", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } }, 1907 { FRV_F_LABELL18, "f-labelL18", 0, 32, 17, 18, { 0, { (1<<MACH_BASE) } } }, 1908 { FRV_F_LABEL24, "f-label24", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } }, 1909 { FRV_F_ICCI_1_NULL, "f-ICCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1910 { FRV_F_ICCI_2_NULL, "f-ICCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1911 { FRV_F_ICCI_3_NULL, "f-ICCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1912 { FRV_F_FCCI_1_NULL, "f-FCCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1913 { FRV_F_FCCI_2_NULL, "f-FCCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1914 { FRV_F_FCCI_3_NULL, "f-FCCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1915 { FRV_F_RS_NULL, "f-rs-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1916 { FRV_F_GRI_NULL, "f-GRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1917 { FRV_F_GRJ_NULL, "f-GRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1918 { FRV_F_GRK_NULL, "f-GRk-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1919 { FRV_F_FRI_NULL, "f-FRi-null", 0, 32, 17, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1920 { FRV_F_FRJ_NULL, "f-FRj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1921 { FRV_F_ACCJ_NULL, "f-ACCj-null", 0, 32, 5, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1922 { FRV_F_RD_NULL, "f-rd-null", 0, 32, 30, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1923 { FRV_F_COND_NULL, "f-cond-null", 0, 32, 30, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1924 { FRV_F_CCOND_NULL, "f-ccond-null", 0, 32, 12, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1925 { FRV_F_S12_NULL, "f-s12-null", 0, 32, 11, 12, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1926 { FRV_F_LABEL16_NULL, "f-label16-null", 0, 32, 15, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1927 { FRV_F_MISC_NULL_1, "f-misc-null-1", 0, 32, 30, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1928 { FRV_F_MISC_NULL_2, "f-misc-null-2", 0, 32, 11, 6, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1929 { FRV_F_MISC_NULL_3, "f-misc-null-3", 0, 32, 11, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1930 { FRV_F_MISC_NULL_4, "f-misc-null-4", 0, 32, 17, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1931 { FRV_F_MISC_NULL_5, "f-misc-null-5", 0, 32, 17, 16, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1932 { FRV_F_MISC_NULL_6, "f-misc-null-6", 0, 32, 30, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1933 { FRV_F_MISC_NULL_7, "f-misc-null-7", 0, 32, 17, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1934 { FRV_F_MISC_NULL_8, "f-misc-null-8", 0, 32, 5, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1935 { FRV_F_MISC_NULL_9, "f-misc-null-9", 0, 32, 5, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1936 { FRV_F_MISC_NULL_10, "f-misc-null-10", 0, 32, 16, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1937 { FRV_F_MISC_NULL_11, "f-misc-null-11", 0, 32, 5, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1938 { FRV_F_LI_OFF, "f-LI-off", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1939 { FRV_F_LI_ON, "f-LI-on", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } }, 1940 { 0, 0, 0, 0, 0, 0, {0, {0}} } 1941 }; 1942 1943 #undef A 1944 1945 1946 1947 /* multi ifield declarations */ 1948 1949 const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD []; 1950 const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD []; 1951 const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD []; 1952 1953 1954 /* multi ifield definitions */ 1955 1956 const CGEN_MAYBE_MULTI_IFLD FRV_F_U12_MULTI_IFIELD [] = 1957 { 1958 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U12_H] } }, 1959 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U12_L] } }, 1960 { 0, { (const PTR) 0 } } 1961 }; 1962 const CGEN_MAYBE_MULTI_IFLD FRV_F_SPR_MULTI_IFIELD [] = 1963 { 1964 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_SPR_H] } }, 1965 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_SPR_L] } }, 1966 { 0, { (const PTR) 0 } } 1967 }; 1968 const CGEN_MAYBE_MULTI_IFLD FRV_F_LABEL24_MULTI_IFIELD [] = 1969 { 1970 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABELH6] } }, 1971 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABELL18] } }, 1972 { 0, { (const PTR) 0 } } 1973 }; 1974 1975 /* The operand table. */ 1976 1977 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) 1978 #define A(a) (1 << CGEN_OPERAND_##a) 1979 #else 1980 #define A(a) (1 << CGEN_OPERAND_/**/a) 1981 #endif 1982 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) 1983 #define OPERAND(op) FRV_OPERAND_##op 1984 #else 1985 #define OPERAND(op) FRV_OPERAND_/**/op 1986 #endif 1987 1988 const CGEN_OPERAND frv_cgen_operand_table[] = 1989 { 1990 /* pc: program counter */ 1991 { "pc", FRV_OPERAND_PC, HW_H_PC, 0, 0, 1992 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_NIL] } }, 1993 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, 1994 /* pack: packing bit */ 1995 { "pack", FRV_OPERAND_PACK, HW_H_PACK, 31, 1, 1996 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_PACK] } }, 1997 { 0, { (1<<MACH_BASE) } } }, 1998 /* GRi: source register 1 */ 1999 { "GRi", FRV_OPERAND_GRI, HW_H_GR, 17, 6, 2000 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRI] } }, 2001 { 0, { (1<<MACH_BASE) } } }, 2002 /* GRj: source register 2 */ 2003 { "GRj", FRV_OPERAND_GRJ, HW_H_GR, 5, 6, 2004 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRJ] } }, 2005 { 0, { (1<<MACH_BASE) } } }, 2006 /* GRk: destination register */ 2007 { "GRk", FRV_OPERAND_GRK, HW_H_GR, 30, 6, 2008 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } }, 2009 { 0, { (1<<MACH_BASE) } } }, 2010 /* GRkhi: destination register */ 2011 { "GRkhi", FRV_OPERAND_GRKHI, HW_H_GR_HI, 30, 6, 2012 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } }, 2013 { 0, { (1<<MACH_BASE) } } }, 2014 /* GRklo: destination register */ 2015 { "GRklo", FRV_OPERAND_GRKLO, HW_H_GR_LO, 30, 6, 2016 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } }, 2017 { 0, { (1<<MACH_BASE) } } }, 2018 /* GRdoublek: destination register */ 2019 { "GRdoublek", FRV_OPERAND_GRDOUBLEK, HW_H_GR_DOUBLE, 30, 6, 2020 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_GRK] } }, 2021 { 0, { (1<<MACH_BASE) } } }, 2022 /* ACC40Si: signed accumulator */ 2023 { "ACC40Si", FRV_OPERAND_ACC40SI, HW_H_ACC40S, 17, 6, 2024 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SI] } }, 2025 { 0, { (1<<MACH_BASE) } } }, 2026 /* ACC40Ui: unsigned accumulator */ 2027 { "ACC40Ui", FRV_OPERAND_ACC40UI, HW_H_ACC40U, 17, 6, 2028 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UI] } }, 2029 { 0, { (1<<MACH_BASE) } } }, 2030 /* ACC40Sk: target accumulator */ 2031 { "ACC40Sk", FRV_OPERAND_ACC40SK, HW_H_ACC40S, 30, 6, 2032 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40SK] } }, 2033 { 0, { (1<<MACH_BASE) } } }, 2034 /* ACC40Uk: target accumulator */ 2035 { "ACC40Uk", FRV_OPERAND_ACC40UK, HW_H_ACC40U, 30, 6, 2036 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACC40UK] } }, 2037 { 0, { (1<<MACH_BASE) } } }, 2038 /* ACCGi: source register */ 2039 { "ACCGi", FRV_OPERAND_ACCGI, HW_H_ACCG, 17, 6, 2040 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGI] } }, 2041 { 0, { (1<<MACH_BASE) } } }, 2042 /* ACCGk: target register */ 2043 { "ACCGk", FRV_OPERAND_ACCGK, HW_H_ACCG, 30, 6, 2044 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ACCGK] } }, 2045 { 0, { (1<<MACH_BASE) } } }, 2046 /* CPRi: source register */ 2047 { "CPRi", FRV_OPERAND_CPRI, HW_H_CPR, 17, 6, 2048 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRI] } }, 2049 { 0, { (1<<MACH_FRV) } } }, 2050 /* CPRj: source register */ 2051 { "CPRj", FRV_OPERAND_CPRJ, HW_H_CPR, 5, 6, 2052 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRJ] } }, 2053 { 0, { (1<<MACH_FRV) } } }, 2054 /* CPRk: destination register */ 2055 { "CPRk", FRV_OPERAND_CPRK, HW_H_CPR, 30, 6, 2056 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } }, 2057 { 0, { (1<<MACH_FRV) } } }, 2058 /* CPRdoublek: destination register */ 2059 { "CPRdoublek", FRV_OPERAND_CPRDOUBLEK, HW_H_CPR_DOUBLE, 30, 6, 2060 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CPRK] } }, 2061 { 0, { (1<<MACH_FRV) } } }, 2062 /* FRinti: source register 1 */ 2063 { "FRinti", FRV_OPERAND_FRINTI, HW_H_FR_INT, 17, 6, 2064 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, 2065 { 0, { (1<<MACH_BASE) } } }, 2066 /* FRintj: source register 2 */ 2067 { "FRintj", FRV_OPERAND_FRINTJ, HW_H_FR_INT, 5, 6, 2068 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, 2069 { 0, { (1<<MACH_BASE) } } }, 2070 /* FRintk: target register */ 2071 { "FRintk", FRV_OPERAND_FRINTK, HW_H_FR_INT, 30, 6, 2072 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, 2073 { 0, { (1<<MACH_BASE) } } }, 2074 /* FRi: source register 1 */ 2075 { "FRi", FRV_OPERAND_FRI, HW_H_FR, 17, 6, 2076 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, 2077 { 0, { (1<<MACH_BASE) } } }, 2078 /* FRj: source register 2 */ 2079 { "FRj", FRV_OPERAND_FRJ, HW_H_FR, 5, 6, 2080 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, 2081 { 0, { (1<<MACH_BASE) } } }, 2082 /* FRk: destination register */ 2083 { "FRk", FRV_OPERAND_FRK, HW_H_FR, 30, 6, 2084 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, 2085 { 0, { (1<<MACH_BASE) } } }, 2086 /* FRkhi: destination register */ 2087 { "FRkhi", FRV_OPERAND_FRKHI, HW_H_FR_HI, 30, 6, 2088 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, 2089 { 0, { (1<<MACH_BASE) } } }, 2090 /* FRklo: destination register */ 2091 { "FRklo", FRV_OPERAND_FRKLO, HW_H_FR_LO, 30, 6, 2092 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, 2093 { 0, { (1<<MACH_BASE) } } }, 2094 /* FRdoublei: source register 1 */ 2095 { "FRdoublei", FRV_OPERAND_FRDOUBLEI, HW_H_FR_DOUBLE, 17, 6, 2096 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, 2097 { 0, { (1<<MACH_BASE) } } }, 2098 /* FRdoublej: source register 2 */ 2099 { "FRdoublej", FRV_OPERAND_FRDOUBLEJ, HW_H_FR_DOUBLE, 5, 6, 2100 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, 2101 { 0, { (1<<MACH_BASE) } } }, 2102 /* FRdoublek: target register */ 2103 { "FRdoublek", FRV_OPERAND_FRDOUBLEK, HW_H_FR_DOUBLE, 30, 6, 2104 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, 2105 { 0, { (1<<MACH_BASE) } } }, 2106 /* CRi: source register 1 */ 2107 { "CRi", FRV_OPERAND_CRI, HW_H_CCCR, 14, 3, 2108 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRI] } }, 2109 { 0, { (1<<MACH_BASE) } } }, 2110 /* CRj: source register 2 */ 2111 { "CRj", FRV_OPERAND_CRJ, HW_H_CCCR, 2, 3, 2112 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ] } }, 2113 { 0, { (1<<MACH_BASE) } } }, 2114 /* CRj_int: destination register */ 2115 { "CRj_int", FRV_OPERAND_CRJ_INT, HW_H_CCCR, 26, 2, 2116 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_INT] } }, 2117 { 0, { (1<<MACH_BASE) } } }, 2118 /* CRj_float: destination register */ 2119 { "CRj_float", FRV_OPERAND_CRJ_FLOAT, HW_H_CCCR, 26, 2, 2120 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRJ_FLOAT] } }, 2121 { 0, { (1<<MACH_BASE) } } }, 2122 /* CRk: destination register */ 2123 { "CRk", FRV_OPERAND_CRK, HW_H_CCCR, 27, 3, 2124 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CRK] } }, 2125 { 0, { (1<<MACH_BASE) } } }, 2126 /* CCi: condition register */ 2127 { "CCi", FRV_OPERAND_CCI, HW_H_CCCR, 11, 3, 2128 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCI] } }, 2129 { 0, { (1<<MACH_BASE) } } }, 2130 /* ICCi_1: condition register */ 2131 { "ICCi_1", FRV_OPERAND_ICCI_1, HW_H_ICCR, 11, 2, 2132 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_1] } }, 2133 { 0, { (1<<MACH_BASE) } } }, 2134 /* ICCi_2: condition register */ 2135 { "ICCi_2", FRV_OPERAND_ICCI_2, HW_H_ICCR, 26, 2, 2136 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_2] } }, 2137 { 0, { (1<<MACH_BASE) } } }, 2138 /* ICCi_3: condition register */ 2139 { "ICCi_3", FRV_OPERAND_ICCI_3, HW_H_ICCR, 1, 2, 2140 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_ICCI_3] } }, 2141 { 0, { (1<<MACH_BASE) } } }, 2142 /* FCCi_1: condition register */ 2143 { "FCCi_1", FRV_OPERAND_FCCI_1, HW_H_FCCR, 11, 2, 2144 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_1] } }, 2145 { 0, { (1<<MACH_BASE) } } }, 2146 /* FCCi_2: condition register */ 2147 { "FCCi_2", FRV_OPERAND_FCCI_2, HW_H_FCCR, 26, 2, 2148 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_2] } }, 2149 { 0, { (1<<MACH_BASE) } } }, 2150 /* FCCi_3: condition register */ 2151 { "FCCi_3", FRV_OPERAND_FCCI_3, HW_H_FCCR, 1, 2, 2152 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCI_3] } }, 2153 { 0, { (1<<MACH_BASE) } } }, 2154 /* FCCk: condition register */ 2155 { "FCCk", FRV_OPERAND_FCCK, HW_H_FCCR, 26, 2, 2156 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FCCK] } }, 2157 { 0, { (1<<MACH_BASE) } } }, 2158 /* eir: exception insn reg */ 2159 { "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6, 2160 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_EIR] } }, 2161 { 0, { (1<<MACH_BASE) } } }, 2162 /* s10: 10 bit signed immediate */ 2163 { "s10", FRV_OPERAND_S10, HW_H_SINT, 9, 10, 2164 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S10] } }, 2165 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, 2166 /* u16: 16 bit unsigned immediate */ 2167 { "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16, 2168 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } }, 2169 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, 2170 /* s16: 16 bit signed immediate */ 2171 { "s16", FRV_OPERAND_S16, HW_H_SINT, 15, 16, 2172 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } }, 2173 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, 2174 /* s6: 6 bit signed immediate */ 2175 { "s6", FRV_OPERAND_S6, HW_H_SINT, 5, 6, 2176 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6] } }, 2177 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, 2178 /* s6_1: 6 bit signed immediate */ 2179 { "s6_1", FRV_OPERAND_S6_1, HW_H_SINT, 11, 6, 2180 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S6_1] } }, 2181 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, 2182 /* u6: 6 bit unsigned immediate */ 2183 { "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6, 2184 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U6] } }, 2185 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, 2186 /* s5: 5 bit signed immediate */ 2187 { "s5", FRV_OPERAND_S5, HW_H_SINT, 4, 5, 2188 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S5] } }, 2189 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, 2190 /* cond: conditional arithmetic */ 2191 { "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1, 2192 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_COND] } }, 2193 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, 2194 /* ccond: lr branch condition */ 2195 { "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1, 2196 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_CCOND] } }, 2197 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, 2198 /* hint: 2 bit branch predictor */ 2199 { "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2, 2200 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } }, 2201 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, 2202 /* hint_taken: 2 bit branch predictor */ 2203 { "hint_taken", FRV_OPERAND_HINT_TAKEN, HW_H_HINT_TAKEN, 17, 2, 2204 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } }, 2205 { 0, { (1<<MACH_BASE) } } }, 2206 /* hint_not_taken: 2 bit branch predictor */ 2207 { "hint_not_taken", FRV_OPERAND_HINT_NOT_TAKEN, HW_H_HINT_NOT_TAKEN, 17, 2, 2208 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_HINT] } }, 2209 { 0, { (1<<MACH_BASE) } } }, 2210 /* LI: link indicator */ 2211 { "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1, 2212 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LI] } }, 2213 { 0, { (1<<MACH_BASE) } } }, 2214 /* lock: cache lock indicator */ 2215 { "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1, 2216 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LOCK] } }, 2217 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, 2218 /* debug: debug mode indicator */ 2219 { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1, 2220 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_DEBUG] } }, 2221 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, 2222 /* ae: all entries indicator */ 2223 { "ae", FRV_OPERAND_AE, HW_H_UINT, 25, 1, 2224 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_AE] } }, 2225 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, 2226 /* label16: 18 bit pc relative address */ 2227 { "label16", FRV_OPERAND_LABEL16, HW_H_IADDR, 15, 16, 2228 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LABEL16] } }, 2229 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } }, 2230 /* label24: 26 bit pc relative address */ 2231 { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24, 2232 { 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } }, 2233 { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } }, 2234 /* A0: A==0 operand of mclracc */ 2235 { "A0", FRV_OPERAND_A0, HW_H_UINT, 17, 1, 2236 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } }, 2237 { 0, { (1<<MACH_BASE) } } }, 2238 /* A1: A==1 operand of mclracc */ 2239 { "A1", FRV_OPERAND_A1, HW_H_UINT, 17, 1, 2240 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } }, 2241 { 0, { (1<<MACH_BASE) } } }, 2242 /* FRintieven: (even) source register 1 */ 2243 { "FRintieven", FRV_OPERAND_FRINTIEVEN, HW_H_FR_INT, 17, 6, 2244 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, 2245 { 0, { (1<<MACH_BASE) } } }, 2246 /* FRintjeven: (even) source register 2 */ 2247 { "FRintjeven", FRV_OPERAND_FRINTJEVEN, HW_H_FR_INT, 5, 6, 2248 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, 2249 { 0, { (1<<MACH_BASE) } } }, 2250 /* FRintkeven: (even) target register */ 2251 { "FRintkeven", FRV_OPERAND_FRINTKEVEN, HW_H_FR_INT, 30, 6, 2252 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, 2253 { 0, { (1<<MACH_BASE) } } }, 2254 /* d12: 12 bit signed immediate */ 2255 { "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12, 2256 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } }, 2257 { 0, { (1<<MACH_BASE) } } }, 2258 /* s12: 12 bit signed immediate */ 2259 { "s12", FRV_OPERAND_S12, HW_H_SINT, 11, 12, 2260 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } }, 2261 { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } }, 2262 /* u12: 12 bit signed immediate */ 2263 { "u12", FRV_OPERAND_U12, HW_H_SINT, 5, 12, 2264 { 2, { (const PTR) &FRV_F_U12_MULTI_IFIELD[0] } }, 2265 { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } } }, 2266 /* spr: special purpose register */ 2267 { "spr", FRV_OPERAND_SPR, HW_H_SPR, 17, 12, 2268 { 2, { (const PTR) &FRV_F_SPR_MULTI_IFIELD[0] } }, 2269 { 0|A(VIRTUAL), { (1<<MACH_BASE) } } }, 2270 /* ulo16: 16 bit unsigned immediate, for #lo() */ 2271 { "ulo16", FRV_OPERAND_ULO16, HW_H_UINT, 15, 16, 2272 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } }, 2273 { 0, { (1<<MACH_BASE) } } }, 2274 /* slo16: 16 bit unsigned immediate, for #lo() */ 2275 { "slo16", FRV_OPERAND_SLO16, HW_H_SINT, 15, 16, 2276 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_S16] } }, 2277 { 0, { (1<<MACH_BASE) } } }, 2278 /* uhi16: 16 bit unsigned immediate, for #hi() */ 2279 { "uhi16", FRV_OPERAND_UHI16, HW_H_UINT, 15, 16, 2280 { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_U16] } }, 2281 { 0, { (1<<MACH_BASE) } } }, 2282 /* psr_esr: PSR.ESR bit */ 2283 { "psr_esr", FRV_OPERAND_PSR_ESR, HW_H_PSR_ESR, 0, 0, 2284 { 0, { (const PTR) 0 } }, 2285 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, 2286 /* psr_s: PSR.S bit */ 2287 { "psr_s", FRV_OPERAND_PSR_S, HW_H_PSR_S, 0, 0, 2288 { 0, { (const PTR) 0 } }, 2289 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, 2290 /* psr_ps: PSR.PS bit */ 2291 { "psr_ps", FRV_OPERAND_PSR_PS, HW_H_PSR_PS, 0, 0, 2292 { 0, { (const PTR) 0 } }, 2293 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, 2294 /* psr_et: PSR.ET bit */ 2295 { "psr_et", FRV_OPERAND_PSR_ET, HW_H_PSR_ET, 0, 0, 2296 { 0, { (const PTR) 0 } }, 2297 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, 2298 /* bpsr_bs: BPSR.BS bit */ 2299 { "bpsr_bs", FRV_OPERAND_BPSR_BS, HW_H_BPSR_BS, 0, 0, 2300 { 0, { (const PTR) 0 } }, 2301 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, 2302 /* bpsr_bet: BPSR.BET bit */ 2303 { "bpsr_bet", FRV_OPERAND_BPSR_BET, HW_H_BPSR_BET, 0, 0, 2304 { 0, { (const PTR) 0 } }, 2305 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, 2306 /* tbr_tba: TBR.TBA */ 2307 { "tbr_tba", FRV_OPERAND_TBR_TBA, HW_H_TBR_TBA, 0, 0, 2308 { 0, { (const PTR) 0 } }, 2309 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, 2310 /* tbr_tt: TBR.TT */ 2311 { "tbr_tt", FRV_OPERAND_TBR_TT, HW_H_TBR_TT, 0, 0, 2312 { 0, { (const PTR) 0 } }, 2313 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } }, 2314 /* sentinel */ 2315 { 0, 0, 0, 0, 0, 2316 { 0, { (const PTR) 0 } }, 2317 { 0, { 0 } } } 2318 }; 2319 2320 #undef A 2321 2322 2323 /* The instruction table. */ 2324 2325 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 2326 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) 2327 #define A(a) (1 << CGEN_INSN_##a) 2328 #else 2329 #define A(a) (1 << CGEN_INSN_/**/a) 2330 #endif 2331 2332 static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = 2333 { 2334 /* Special null first entry. 2335 A `num' value of zero is thus invalid. 2336 Also, the special `invalid' insn resides here. */ 2337 { 0, 0, 0, 0, {0, {0}} }, 2338 /* add$pack $GRi,$GRj,$GRk */ 2339 { 2340 FRV_INSN_ADD, "add", "add", 32, 2341 { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2342 }, 2343 /* sub$pack $GRi,$GRj,$GRk */ 2344 { 2345 FRV_INSN_SUB, "sub", "sub", 32, 2346 { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2347 }, 2348 /* and$pack $GRi,$GRj,$GRk */ 2349 { 2350 FRV_INSN_AND, "and", "and", 32, 2351 { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2352 }, 2353 /* or$pack $GRi,$GRj,$GRk */ 2354 { 2355 FRV_INSN_OR, "or", "or", 32, 2356 { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2357 }, 2358 /* xor$pack $GRi,$GRj,$GRk */ 2359 { 2360 FRV_INSN_XOR, "xor", "xor", 32, 2361 { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2362 }, 2363 /* not$pack $GRj,$GRk */ 2364 { 2365 FRV_INSN_NOT, "not", "not", 32, 2366 { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2367 }, 2368 /* sdiv$pack $GRi,$GRj,$GRk */ 2369 { 2370 FRV_INSN_SDIV, "sdiv", "sdiv", 32, 2371 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } 2372 }, 2373 /* nsdiv$pack $GRi,$GRj,$GRk */ 2374 { 2375 FRV_INSN_NSDIV, "nsdiv", "nsdiv", 32, 2376 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } 2377 }, 2378 /* udiv$pack $GRi,$GRj,$GRk */ 2379 { 2380 FRV_INSN_UDIV, "udiv", "udiv", 32, 2381 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } 2382 }, 2383 /* nudiv$pack $GRi,$GRj,$GRk */ 2384 { 2385 FRV_INSN_NUDIV, "nudiv", "nudiv", 32, 2386 { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } 2387 }, 2388 /* smul$pack $GRi,$GRj,$GRdoublek */ 2389 { 2390 FRV_INSN_SMUL, "smul", "smul", 32, 2391 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } 2392 }, 2393 /* umul$pack $GRi,$GRj,$GRdoublek */ 2394 { 2395 FRV_INSN_UMUL, "umul", "umul", 32, 2396 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } 2397 }, 2398 /* smu$pack $GRi,$GRj */ 2399 { 2400 FRV_INSN_SMU, "smu", "smu", 32, 2401 { 0, { (1<<MACH_FR400), UNIT_IACC, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } 2402 }, 2403 /* smass$pack $GRi,$GRj */ 2404 { 2405 FRV_INSN_SMASS, "smass", "smass", 32, 2406 { 0, { (1<<MACH_FR400), UNIT_IACC, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } 2407 }, 2408 /* smsss$pack $GRi,$GRj */ 2409 { 2410 FRV_INSN_SMSSS, "smsss", "smsss", 32, 2411 { 0, { (1<<MACH_FR400), UNIT_IACC, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } 2412 }, 2413 /* sll$pack $GRi,$GRj,$GRk */ 2414 { 2415 FRV_INSN_SLL, "sll", "sll", 32, 2416 { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2417 }, 2418 /* srl$pack $GRi,$GRj,$GRk */ 2419 { 2420 FRV_INSN_SRL, "srl", "srl", 32, 2421 { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2422 }, 2423 /* sra$pack $GRi,$GRj,$GRk */ 2424 { 2425 FRV_INSN_SRA, "sra", "sra", 32, 2426 { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2427 }, 2428 /* slass$pack $GRi,$GRj,$GRk */ 2429 { 2430 FRV_INSN_SLASS, "slass", "slass", 32, 2431 { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } 2432 }, 2433 /* scutss$pack $GRj,$GRk */ 2434 { 2435 FRV_INSN_SCUTSS, "scutss", "scutss", 32, 2436 { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } } 2437 }, 2438 /* scan$pack $GRi,$GRj,$GRk */ 2439 { 2440 FRV_INSN_SCAN, "scan", "scan", 32, 2441 { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2442 }, 2443 /* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */ 2444 { 2445 FRV_INSN_CADD, "cadd", "cadd", 32, 2446 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2447 }, 2448 /* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */ 2449 { 2450 FRV_INSN_CSUB, "csub", "csub", 32, 2451 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2452 }, 2453 /* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */ 2454 { 2455 FRV_INSN_CAND, "cand", "cand", 32, 2456 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2457 }, 2458 /* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */ 2459 { 2460 FRV_INSN_COR, "cor", "cor", 32, 2461 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2462 }, 2463 /* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */ 2464 { 2465 FRV_INSN_CXOR, "cxor", "cxor", 32, 2466 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2467 }, 2468 /* cnot$pack $GRj,$GRk,$CCi,$cond */ 2469 { 2470 FRV_INSN_CNOT, "cnot", "cnot", 32, 2471 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2472 }, 2473 /* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */ 2474 { 2475 FRV_INSN_CSMUL, "csmul", "csmul", 32, 2476 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } 2477 }, 2478 /* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */ 2479 { 2480 FRV_INSN_CSDIV, "csdiv", "csdiv", 32, 2481 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } 2482 }, 2483 /* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */ 2484 { 2485 FRV_INSN_CUDIV, "cudiv", "cudiv", 32, 2486 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } 2487 }, 2488 /* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */ 2489 { 2490 FRV_INSN_CSLL, "csll", "csll", 32, 2491 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2492 }, 2493 /* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */ 2494 { 2495 FRV_INSN_CSRL, "csrl", "csrl", 32, 2496 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2497 }, 2498 /* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */ 2499 { 2500 FRV_INSN_CSRA, "csra", "csra", 32, 2501 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2502 }, 2503 /* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */ 2504 { 2505 FRV_INSN_CSCAN, "cscan", "cscan", 32, 2506 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2507 }, 2508 /* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ 2509 { 2510 FRV_INSN_ADDCC, "addcc", "addcc", 32, 2511 { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2512 }, 2513 /* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ 2514 { 2515 FRV_INSN_SUBCC, "subcc", "subcc", 32, 2516 { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2517 }, 2518 /* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ 2519 { 2520 FRV_INSN_ANDCC, "andcc", "andcc", 32, 2521 { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2522 }, 2523 /* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ 2524 { 2525 FRV_INSN_ORCC, "orcc", "orcc", 32, 2526 { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2527 }, 2528 /* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ 2529 { 2530 FRV_INSN_XORCC, "xorcc", "xorcc", 32, 2531 { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2532 }, 2533 /* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ 2534 { 2535 FRV_INSN_SLLCC, "sllcc", "sllcc", 32, 2536 { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2537 }, 2538 /* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */ 2539 { 2540 FRV_INSN_SRLCC, "srlcc", "srlcc", 32, 2541 { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2542 }, 2543 /* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */ 2544 { 2545 FRV_INSN_SRACC, "sracc", "sracc", 32, 2546 { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2547 }, 2548 /* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */ 2549 { 2550 FRV_INSN_SMULCC, "smulcc", "smulcc", 32, 2551 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } 2552 }, 2553 /* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */ 2554 { 2555 FRV_INSN_UMULCC, "umulcc", "umulcc", 32, 2556 { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } 2557 }, 2558 /* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ 2559 { 2560 FRV_INSN_CADDCC, "caddcc", "caddcc", 32, 2561 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2562 }, 2563 /* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ 2564 { 2565 FRV_INSN_CSUBCC, "csubcc", "csubcc", 32, 2566 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } } 2567 }, 2568 /* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */ 2569 { 2570 FRV_INSN_CSMULCC, "csmulcc", "csmulcc", 32, 2571 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } } 2572 }, 2573 /* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */ 2574 { 2575 FRV_INSN_CANDCC, "candcc", "candcc", 32, 2576 { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL,